Machine Learning (ML) has taken the world by storm, with applications spanning entertainment, bio-medicine, surveillance, and even data compression. Among the many ML techniques, Deep Neural Networks (DNNs) stand out for their high performance. However, this comes at the cost of significant computational complexity (translating to substantial memory requirements depending on the application). Given these challenges, research into DNN compression has naturally emerged. NNCodec is a quantization plus arithmetic-coding-based standard that compresses the weights of DNNs. In scenarios where energy efficiency and performance are critical, a hardware implementation of NNCodec becomes highly desirable, particularly as an alternative to software-based solutions. Within this context, this work presents assessments of the NNCodec tool regarding compression efficiency and quantized weight distribution among some commonly used DNNs on the encoder side. Next, a hardware design is introduced, named DeepBinArch, whose purpose is to implement the first step of the arithmetic encoding lossless stage on the encoder, more specifically, the Binarization step of the algorithm. The design is presented in detail, being the first ever found in the literature to the best of the authors’ knowledge.
As CMOS technology reaches its physical limits, alternative technologies such as Silicon Dangling Bonds (SiDBs) offer promising solutions for higher performance, lower thermal output and higher energy efficiency. While significant advancements have been made in logic gates and electrostatic modeling, analysis of SiDB-based wires remain underexplored. This paper presents methodologies for analyzing wire performance in SiDB technology, evaluating various wire configurations (vertical, horizontal, diagonal) and examining their operational domains, working critical temperatures, and performance boundaries. Key contributions includes experimental scripts for the Fiction Framework, a comprehensive collection of wire configurations based on literature, and an in-depth analysis of wire performance. The results aim to advance scalability and reliability of SiDB circuits, addressing a critical gap in the field.
Digital video processing is generally a computationally intensive task due to the large volume of data involved and the growing demand for highly efficient compression, especially for high-resolution formats increasingly common in the market. Given these characteristics, this paper proposes an approach based on Machine Learning techniques aimed at accelerating the Fractional Motion Estimation process in the AOMedia Video 1 (AV1) codec. The proposed method involves predicting the best filter combination among nine available options, using a model composed of decision trees. A total of eight decision trees were implemented and strategically organized according to the selection priorities defined by the AV1 video codec. The proposed solution achieved a time reduction of $\mathbf{2 . 4 2 \%}$ with a corresponding efficiency loss of $0.11 \%$.
RISC-V open architecture and flexibility make it a choice for embedded devices, where efficient encryption is essential for ensuring data security with minimal resource overhead. The objective of this work is to conduct a power-performance-area (PPA) evaluation of the Zkne Instruction Set Extension (ISE) for the Advanced Encryption Standard (AES) algorithm on a RISC-V processor. This evaluation uses synthesis and simulation metrics to demonstrate efficiency improvements, including area and energy costs, clock cycles, and performance monitoring registers. To analyze the impact of Zkne ISE on encryption and decryption performance, standard and extended implementations of AES are assessed on the RISC-V, using an optimized AES algorithm with T-tables, together with the TinyCrypt reference software. Results demonstrate that Zkne significantly reduces execution time and energy per operation, validating its suitability for secure and efficient cryptographic processing in resource-constrained environments.
This work investigates the reliability of flight software for a case-study mission based on NASA’s Core Flight System (cFS) running on a RISC-V microprocessor. Radiationinduced faults are emulated in software and can affect the microprocessor’s register file as well as all addressable volatile memory. Benchmark applications embedded in the flight software are used as probes to monitor the correct operation of flight software services. A fault injection campaign was conducted to identify the most sensitive memory regions storing software data and to analyze the distribution of failures across the flight software tasks. In approximately $79 \%$ of the functional failures, the flight software became unresponsive, leading to a communication timeout. In $9 \%$ of the failures, the flight software remained active, but at least one benchmark application became unresponsive. Finally, in approximately $12 \%$ of the failures, the benchmark applications transmitted incorrect results. Additionally, by leveraging FreeRTOS task trace resources, it was possible to determine which task was executing at the moment each functional failure was detected, identifying the flight software’s Scheduler Application (SCH) as the task that failed most frequently.
This work presents a survey of power amplifiers designed in complementary metal-oxide semiconductors (CMOS) in the X-Band, as part of the new and promising frequency region, defined as upper-mid band, for the sixth generation of mobile communications (6G). The paper presents some of the key visions and concepts related to 6G, discusses the advantages and use of the upper-mid band and presents the survey of power amplifiers designed in the frequency range between 8 GHz 12 GHz. Also, it discusses the state-of-art and compares the compression output power with the expected output power for user equipments for link budget scenarios. With an average of 3.5 GHz of operating bandwidth, the surveyed PAs establish an efficiency target up to $25 \%$, but few attended to the expected linear output power, indicating an improvement demand in the literature of CMOS PAs in the X-Band.
Standard cells are the core of digital Very Large Scale Integration designs. As technology scales beyond 7nm nodes, the increased layout design complexity and resource limitation have driven research into automating cell generation. Among these efforts, sequential place and route approaches are the most prominent. However, computing a routable placement remains the most time-consuming step. To address this challenge, this paper proposes an image-based routability predictor for standard cell placement. The CNN model was trained and evaluated on a dataset comprising 16,235 transistor placements drawn from 690 standard cell designs, achieving prediction accuracies of $\mathbf{9 6 . 3 2 \%}$ for single-height and $\mathbf{9 3 . 5 1 \%}$ for double-height configurations.
This work investigates the selective integration of radiation-hardening inverter topologies into arithmetic circuits of a RISC-V architecture, aiming to improve system resilience against soft errors with minimal overhead. Five inverter designs: Standard, Strengthening, Pseudo-Strengthening, Schmitt Trigger and Rad-Hard, were modeled at the transistor level and analyzed through electrical simulations for delay and energy metrics. These inverters were then integrated into full adder cells to evaluate their impact on performance and robustness. The most promising design, Rad-Hard, was further incorporated into the RS5 processor, a RISC-V implementation, and synthesized using both 45 nm CMOS and 7 nm FinFET technologies to assess its area and power trade-offs. The higher impact in area is observed on 7 nm, with $16.7 \%$ increase in transistor count, a marginal increase of $0.73 \%$ in the ALU and only $0.031 \%$ in the complete RS5 processor. This demonstrates that robust circuit design can be achieved with minimal impact on the overall silicon area, even in advanced technology nodes.
This paper presents the design of a fully integrated 1 MHz clock reference, using the GF180MCU open-source PDK. The proposed circuit uses an RC relaxation topology; post-layout simulations presented a central frequency of 1.084 MHz with a temperature coefficient of $24 \mathrm{ppm} /^{\circ} \mathrm{C}$ over a temperature range of $-20^{\circ} \mathrm{C}$ to $120^{\circ} \mathrm{C}$ with a 3.3 V supply voltage, in process and mismatch Monte Carlo simulations the frequency standard deviation was $6.3 \%$ of the average, using an area of $0.0065 \mathrm{~mm}^{2}$, and consuming 0.26 mW.
This work presents a non-intrusive, lightweight machine-learning-driven approach for runtime detection of Hardware Trojan (HT) in NoC-based manycore systems. The proposed solution uses XGBoost to detect subtle traffic anomalies caused by such HTs. Unlike previous works, which often rely on offline inference or expensive hardware modifications, this approach is implemented as a software-based runtime detection model and assessed on a Register Transfer Level (RTL)-modeled platform. The results show an average detection rate of $92 \%$ in real applications with low overheads, making it a feasible solution for runtime security in manycore systems.
Analog and mixed-signal (AMS) integrated circuit (IC) design is essential for modern SoC development in applications such as AI, IoT, and robotics. However, AMS design remains largely manual, requiring engineers to navigate multiple abstraction levels and complex iterations. Traditional engineering education rarely equips students with the skills needed for this challenge. In this paper, we propose a set of tapeout-focused strategies for AMS education based on open-source tools and full-chip design flows. Drawing on over three years of experience at AC3E-USM in Chile, we outline an educational approach combining programmatic design, collaborative version control, and real fabrication timelines. We highlight student participation in global initiatives like the SSCS Chipathon and IHP multi-project runs, supported by resources such as the SKY130 and IHP open-source PDKs, Docker-based flows, and GitHub-based team coordination. Two case studies demonstrate how this approach enables meaningful hands-on learning and fosters a foundation for regional academic–industry collaboration in the global semiconductor ecosystem.
This paper presents the silicon-validated implementation of synchronous and asynchronous Frequency-to-Digital Converters (FDCs), designed entirely using open-source Electronic Design Automation (EDA) tools and fabricated via the Tiny Tapeout multi-project wafer (MPW) service using the SKY130 PDK. Both architectures are fully digital and based on counter-based frequency measurement, with the synchronous and asynchronous versions employing edge-sampled registers and using ripple counters with independent clocks, respectively. Implemented within a $160 \times 100 \mu \mathrm{~m}^{2}$ tile, the designs achieved $8.3 \%$ standard cell area utilization, exhibited dynamic power consumption below $21 \mu \mathrm{~W}$, and operated correctly at clock frequencies up to 180.5 MHz based on post-layout signoff analysis. Developed as part of an undergraduate IC design course, this work demonstrates the feasibility of full-cycle silicon prototyping using only open-source tools and highlights the educational value of such methodologies in academic environments.
The Affine Motion Estimation (AME) is one of the new tools of the Versatile Video Coding (VVC) standard. The AME contribution to the coding efficiency comes with a high computational cost, especially for real-time high-resolution video encoding, making the employment of dedicated hardware mandatory for battery-powered devices. To be able to reach a high processing rate and high efficiency in area utilization and power dissipation, the proposed architecture reduced the gradient-based iterative algorithm to three iterations, with this optimization having a BD-Rate increase of only $\mathbf{0. 9 2 \%}$. Considering these optimizations, this work presents a dedicated hardware design for the Affine Gradient-Based Search of the VVC standard, with a focus on real-time UHD 4K video processing. ASIC synthesis results of the proposed design, synthesized using TSMC 40 nm standard cells technology, show a circuit area of 728 K gates, with a power dissipation of 54.70 mW when targeting the processing of UHD 4K@60fps videos.
This paper proposes a dynamic approximate storage scheme for VVC intra-frame prediction, which adjusts memory operations precision according to frame importance within the Random Access structure. Focusing on the critical storage for reconstructed and original samples, the study analyzes intraframe prediction demands across different frame levels. Our scheme is based on an approximate memory system, which employs data approximation due to a dynamic voltage scaling SRAM chip. The proposed approach dynamically allocates higher precision to key frames while permitting greater approximation in less critical ones. Experimental results show that this strategy reduces coding efficiency losses by up to $8.2 \%$ in BD-Rate compared to static approximation, with a maximum increase of $7.70 \%$ over the lossless baseline, while still achieving energy savings of up to $\mathbf{5 4 \%}$.
Reusable verification solutions are paramount for modern digital IC design workflows, with Universal Verification Methodology (UVM) being the industry-standard approach for testbenches of complex IP and SoC designs. However, the availability of high-quality verification IP remains limited, particularly for open-source silicon and academic projects. In this context, this work presents the development of an open-access UVM VIP for the AXI-Stream interface using SystemVerilog. The UVM agent, environment and scoreboard presented are reusable and configurable components for verifying RTL designs that utilize the AXI4-Stream, a point-to-point unidirectional protocol for data streams in SoC interconnects part of the ARM AMBA bus standards. The developed VIP was analyzed in a case study with an open-source AXI-Stream FIFO IP, achieving $100 \%$ functional coverage in all covergroups defined for verification of protocol compliance.
Traditional strong Physical Unclonable Functions (PUFs) are vulnerable to modeling attacks using Machine Learning (ML). To address this issue, this paper proposes a strong PUF structure with resistance to modeling attacks based on Dynamic Obfuscation (DO), composed of Linear Feedback Shift Registers (LFSRs), PUFs, and several logic gates. The characteristics of DO are as follows: (1) the initial state of the LFSR is determined by the PUF’s response, making it uncontrollable; (2) the updated state of the LFSR determines the obfuscated bit of each input challenge, achieving a dynamic mapping between challenges and responses. An Arbiter PUF (APUF) based on DO has been implemented on Xilinx Artix-7 FPGA development boards, and experimental results show that the structure can effectively resist modeling attacks from various ML algorithms, with prediction accuracy close to $\mathbf{5 0 \%}$.
This paper investigates the impact of register reservation techniques on the radiation resilience of Arm Cortex-M7 microprocessors. Using a $32 \times 32$ matrix multiplication workload, we evaluate performance and reliability across several compilation configurations, focusing on standard compilation and versions reserving up to 7 general-purpose registers. Neutron irradiation experiments were conducted at the GENESIS facility to assess fault behavior under realistic space conditions. Additionally, a full instruction-level trace analysis was performed to understand the implications of register reservation. Results show that while reserving a few registers introduces modest execution overhead, it significantly shifts the fault outcome profile without initially degrading overall reliability. However, excessive reservation leads to noticeable reliability degradation. These findings provide insight into the interplay between compiler constraints and system robustness, establishing a foundation for future software-level hardening strategies.
The increasing integration of electronic systems in critical applications has made the prediction and mitigation of circuit aging effects a key challenge for ensuring longterm reliability. Traditional solutions such as guard-banding compromise performance, power, area and ultimately cost, highlighting the need for better solutions. This work proposes a selftuning on-chip aging sensor capable of accurately tracking inmission critical path time slack erosion, without the need for manual recalibration. The proposed solution enhances a baseline sensor architecture by incorporating a dynamic phase shift mechanism for autonomous slack detection during operation. The sensor was implemented in an FPGA and validated using a comprehensive experimental commercial platform, enabling controlled variation of supply voltage, core temperature, and accelerated aging through burn-in stress. Experimental results showed that the sensor tracks path delay increase under voltage reduction and temperature rise, while continuously monitoring aging effects. Functional failures were observed shortly after the sensor indicated a time slack approaching zero and so, confirming its predictive capability. This approach allows in-mission mode aging monitoring, which is a paramount condition for Silicon Lifecycle Management (SLM) strategies.
In the context of RF energy harvesting (EH), it is necessary to ensure appropriate matching between the harvester’s antenna and the RF power source, often unknown or varying by orders of magnitude according to the EH environment. This dynamic matching, also known as Maximum Power Point Tracking (MPPT), can be improved using capacitive adjustment networks, controlled by a system that monitors the derivative of the voltage stored in a capacitor. Such application requires a low-power differentiator capable of measuring slow charging slopes, in the order of a few V/s. It is not trivial to implement low-power, stable differentiators, as they usually rely on resistors that are large, noisy, or lead to a high power consumption. In this work, we propose a resistorless topology designed to measure small, positive derivatives in the range of 0-2 V/s, with a DC power consumption of 120 nW, while improving noise performance by $4 \times$ and reducing output voltage variation in mismatch by nearly $14 \times$ compared to the state-of-the-art. Our circuit also demonstrates improved rejection against fluctuations in its supply voltage, which are unavoidable in EH systems.
