In today's mobile computers, such as tablets and smart phones, power, performance and chip area are the major constraints to the development of cost efficient high tech products. One solution is the usage of application-specific instruction-set processors (ASIP), which are optimized for the execution of special tasks and thus enable a more efficient implementation. As an extension to this approach the LISPARC processor is developed. For more flexibility, the LISPARC model enables dynamic reconfiguration at run-time in order to adapt to different ASIPs. The processor model of LISPARC is described using an architecture description language called Language for Instruction-Set Architectures (LISA).

Adaptation of hardware in relation to the requirements of a specific application is well known and investigated in the domain of Field Programmable Gate Arrays (FPGA) based reconfigurable system architectures. In these system approaches, a number of predefined blocks, mainly accelerators for processors, are loaded from an external storage and are transferred to the FPGA configuration memory in order to manipulate the on-chip functionality. A novel approach is to adapt the microarchitecture of a processor in order to achieve a temporal application-specific behavior. In combination with the well known techniques of dynamic reconfiguration of a FPGA, novel degrees of freedom are available for an energy efficient run-time dynamic system approach.This paper presents one adaptation mechanism, in which the pipeline depth is adapted according to the control flow and data flow of an application. The concept and also the realization are described and evaluated in terms of efficiency with some benchmarks.

The exponential increase of CMOS circuit complexity along the last decades has lead to two growing problems. The increasing Non-recurring Engineering (NRE) costs of ASICs or System-on-Chips are becoming only affordable to the highest volume applications. Additionally the design methodologies have not kept pace with the rising complexity leading to a rising design productivity gap. Research into reconfigurable architectures and NoC (Network-on-Chip) communication systems have shown paths for mitigating these problems for lower volume applications. In this paper, we present the European Integrated Project MORPHEUS (IST 027342). It advocates an innovative approach of heterogeneous, dynamically reconfigurable SoCs consisting of accelerators of various reconfiguration granularity connected by a NoC and supported by an integrated toolset for spatial and sequential design. The power of this approach is demonstrated with four applications from the industrial environment.

General purpose processors provide a well performance with adequate power consumption for a huge bandwidth of applications in average. However, most embedded systems target a very narrow or even single application domain which would benefit from a specific processor, optimized for this scenario in order to gain performance and to reduce power consumption. But the development of application specific processors for each application is a time consuming task and often not feasible for developers due to the missing toolsets or experience in processor design. This paper introduces a novel approach for a processor core, which is able to adapt its micro architecture in relation to the application requirement. In general, the processor starts in a general purpose mode and migrates while run-time to a special purpose processor by adapting its micro architecture. The paper introduces this novel processor approach which is called i-core and presents first experimental results.

The exponential increase of CMOS circuit complexity has opened the way to the introduction of new capabilities and functionalities into electronic systems that have been sources of innovations in major growth markets. To pursue this trend all along the last decades, major evolutions of design methodologies and computing architectures have been necessaries to master this complexity. Now, increasing Non-Recurrent Engineering (NRE) costs have made the design of ASICs or System-on-Chips unaffordable for a broad class of applications, whose the low-volume markets are insufficient to make them economically viable. But, use of Commercial Off-The-Shelf (COTS) boards is not always satisfactory due to the low power-efficiency of general-purpose processors and the complexity of programming FPGAs. We thus advocate for a new class of System-on-Chips, composed of a mix of processors as well as very flexible and easily programmable accelerators in order to cope with increasing NRE costs and tight time-to-markets. In this perspective, reconfigurable architectures are very appealing for their trade-off between the performance of ASICs and the flexibility of general-purpose processors. This chapter presents an innovative approach of a dynamically reconfigurable heterogeneous platform, called MORPHEUS and which consists of a System-on-Chip integrating different kinds of reconfigurable accelerators controlled by a general-purpose processor.

The relentless increase in capacity of Field-Programmable Gate-Arrays (FPGAs) has made them vehicles of choice for both prototypes and final products requiring on-chip multi-core, heterogeneous and reconfigurable systems. Multiple cores can be embedded as hard- or soft-macros, have customizable instruction sets, multiple distributed RAMs and/or configurable interconnections. Their flexibility allows them to achieve orders of magnitude better performance than conventional computing systems via customization. Programming these systems, however, is extremely cumbersome and error-prone and as a result their true potential is only achieved very often at unreasonably high design efforts. This project covers developing, implementing and evaluating a novel compilation and synthesis system approach for FPGA-based platforms. We rely on Aspect-Oriented Specifications to convey critical domain knowledge to a mapping engine while preserving the advantages of a high-level imperative programming paradigm in early software development as well as program and application portability. We leverage Aspect-Oriented specifications and a set of transformations to generate an intermediate representation suitable to hardware mapping. A programming language, LARA, will allow the exploration of alternative architectures and design patterns enabling the generation of flexible hardware cores that can be easily incorporated into larger multi-core designs. We will evaluate the effectiveness of the proposed approach using partner-provided codes from the domain of audio processing and real-time avionics. We expect the technology developed in REFLECT to be integrated by our industrial partners, in particular by ACE, a leading compilation tool supplier for embedded systems, and by Honeywell, a worldwide solution supplier of embedded high-performance systems.

The Intel Single Chip Cloud Computer (SCC) architecture offers the adjustment of voltage and frequency on individual islands in a certain range and in a certain dependability to each other. This possibility offers a high degree of freedom for workload balancing which can be done statically (at compile time) or dynamically (at run-time). Especially the latter topic, the dynamic voltage and frequency scaling (DVFS) is of high interest for novel multiprocessor systems, if they are deployed in energy efficient systems. It enables to provide computing performance on demand and therefore reduces power consumption. We envision to develop models, methods and cost functions for the DVFS in order to optimize the workload balance of all processor cores at run-time on the SCC.

This Chapter describes the mechanisms used to control the dynamic reconfiguration aspects of the MORPEUS system. The base is formed by a realtime operating system and is topped by an allocation and scheduling system for reconfigurable operations.

Reconfigurable architectures and NoC (network-on-chip) communication systems have introduced new research directions for technology and flexibility issues, which have been largely investigated in the last decades. Exploiting the flexibility of reconfigurable architectures, the run-time adap-tivity through run-time reconfiguration, opens a new area of research by considering dynamic reconfiguration. Since software parts of an embedded system can also be included into reconfigurable hardware by integration of an IP-based microcontroller, the reconfigurable architecture provides a flexible, multi-adaptive heterogeneous platform forHW/SW co-design. In this paper, we present the European integrated project MORPHEUS (1ST 027342). Its goal is to develop new heterogeneous reconfigurable SoCs with various sizes of reconfiguration granularity and to provide an integrated toolset of spatial and sequential design that can be used for mapping and execution of the target applications. Additionally a NoC approach is included in order to demonstrate the mentioned benefits and scalability for actual and future SoC design. The power of this approach will be demonstrated with four applications from the industrial environment.

This paper presents an integrated programming toolset for application implementation on an heterogeneous reconfigurable architecture. The objectives of the toolset are to optimize the application implementation productivity and to enable the dynamic reconfiguration on reconfigurable units of the target architecture. The proposed solution is based on the combination of a compilation concept permitting to call function implemented on these reconfigurable units, an operating system dynamically managing the units reconfigurations, a formal specification tool and a design tool for the implementation of the accelerated functions. The paper gives an overview of these tools, that are combined to take benefit of their facilitated reciprocal interactions.