RF frequency filters employing acoustic-wave resonators are used in common modern handsets for mobile communication. These resonators make use of the piezoelectric effect, i.e. their characteristics therefore strongly depend on employed materials and technology and comprise relatively fixed behavior. Classic filter design theory, however, is dealing with lumped reactive elements like inductors and capacitors for the realization of any-order filter designs instead. This theoretical treatment can lead to a multitude of realizable designs which makes it in fact very generous but also complex. Furthermore, theory is well-known and resulting structures are excessively explored in practice. In this paper, a new practical approach for the combination of these two filter types, preserving their respective benefits, is presented.

This paper focuses on theoretical investigations on "Acoustic-Wave-Lumped-Element Resonator" (AWLR) modules that have gained much interest in the last few years regarding general progress in radio frequency (RF) filter techniques and design. It is shown how the bandwidth characteristics depend on the electro-mechanical coupling factor of the employed piezoelectric material. General approximation formulas for the achievable 3 dB-bandwidth and for the maximum achievable bandwidth of symmetric AWLR modules are given. The results of the mathematical derivation are verified by simulation.

This work proposes the improvement of the RF transceiver front-end based on the integration of passive components using modern SiP technologies. The investigation of two passive impedance matching networks for a SCPA are presented as low-cost high-performance alternatives for a 28 nm CMOS Matching Network (MN). The design was validated by FEM simulations and implemented for the first case in 130 nm SOI technology, and for the second case in 3-layer core-less package technology. The SOI implementation provides a peak output power of 16 dBm, presents an Insertion Loss (IL) of 2dB. The package implementation provides a peak output power of 19 dBm and an IL of 0.6dB. Measurement results show that the Silicon-on-Insulator (SOI) implementation offers in a Switched Capacitor Power Amplifier (SCPA) peak efficiency of 18% while the implementation with in-package matching network offers a peak efficiency 38 %.

The evolving trend for increasing data rates in cellular communication systems with limited and fragmented frequency spectrum requires enhanced spectral efficiency of today's and future communication standards. The resulting need for high-order modulation schemes with large peak-to-average power ratio results in stringent requirements on in-channel linearity and SNR. At the same time FDD operation in SAW filter-less designs enforces very demanding limits for out-of-band and spurious emissions. Digital polar TX concepts have demonstrated low power consumption combined with low out-of-band noise in moderate bandwidth applications like WCDMA [1]. However, the implementation of 4G wideband polar systems with 20MHz RF bandwidth and above is very challenging due to the nonlinear conversion from cartesian to polar coordinates extending the effective signal bandwidth even further. A digital quadrature TX concept with up to 80MHz bandwidth, low EVM and moderate power efficiency has been shown in [2]. More than 30% power-added efficiency has been demonstrated in a 20MHz polar TX based on a switched-capacitor digital PA [3]. However, [2,3] suffer from low resolution and limited out-of-band noise performance.

The increasing complexity and cost pressure of advanced radios for mobile communication devices dictates further integration of front-end components into the transceiver (TRX) in order to reduce bill-of-material (BoM), printed-circuit-board (PCB) area and system cost. In [1] a fully-digital polar modulator is presented, which enables a SAW-less 2G/3G transmitter, in particular by solving the transmitter (TX) noise in receive (RX) band issues at various duplex distances (45/80/190/400MHz). Removing the TX SAW filter by adopting innovative transmitter topologies not only reduced the amount of external components, but also paved the way for monolithic power amplifier (PA) integration into the CMOS transceiver IC. This step poses additional challenges in terms of RX-TX cross-talk, self-heating and remodulation (unwanted frequency modulation of local oscillator by modulated output signal, very critical in IQ direct modulators, much less pronounced in polar modulators). The first integration of a PA with external matching network into a TRX SoC product has been presented in [2] for DECT cordless phones using GFSK modulation. PAs are also successfully integrated into a Wi-Fi TRX SoC, delivering linear transmit power up to 22dBm [3]. Following these earlier examples, this work proposes to fully integrate a PA capable of delivering more than 0.5W of linear RF power for the demanding 3G cellular applications.

Simultaneously achieving high linearity and high power-added efficiency (PAE) is essential for power amplifiers (PA) operating with modern communication signals. The challenge is exacerbated by the low breakdown voltages of standard CMOS realizations. This work presents a low-complexity programmable analog scheme to compensate the strong AM-AM and AM-PM nonlinearities of the high-ruggedness stacked-cascode topology while maintaining high PAE. The proposed solution utilizes standard NMOS devices to achieve peak PAE of 60% at the 900 MHz band from a 3V supply. The compensation scheme manages to improve the output 1-dB compression point by up to 2 dB and keep the AM-PM variation within 5 degrees. The proposed method improves the linear output power (@ ACPR= -40 dBc) for a Class-AB power amplifier by up to 1.5 dB without compromising PAE or saturated output power.

The suitability of an RF power amplifier (PA) for modern sophisticated modulation schemes demands high linearity. One of the most significant figures of merit concerning PA linearity is its adjacent channel power ratio (ACPR). The aim of this paper is to propose a time-efficient simulation procedure for ACPR which conforms with the latest 3GPP TS 25.101 specifications for its calculation. This procedure overcomes the time penalty associated with the traditional envelope-based simulation method. The approach is based on standard harmonic balance (HB) tools with MATLAB post-processing incorporating the Overlap-add (OLA) signal decomposition DSP technique for fast RRC filtering. In addition, the simulation results are compared with measurements of a commercial WCDMA PA for verification. Accuracies of better than 0.5dB and 1.1dB are achieved up to 10dB and 2dB backoff respectively.

A novel, high ruggedness power amplifier topology in a 65-nm CMOS technology is proposed. The proposed stacked cascode topology uses only standard devices available in a modern triple-well CMOS process to achieve breakdown voltages of more than 18V. The power amplifier stage delivers 28 dBm output power at a power-added efficiency (PAE) of 69.9% from a 3.6V supply. The saturation gain is 18 dB. A watt-level power amplifier for GSM low-band operation with 31-dBm output power and 61% PAE is presented.