CMOS silicon on insulator technology has shown its ability to process hardened components which remain functional after irradiation with a total dose of several tens of Megarads. New tests on elementary transistors and 29101 microprocessor have been made at doses up to 100 Mrad(SiO/sub 2/) and above. Results of irradiation at these total doses are presented for different biases, together with the post-irradiation behaviour of the components. All the observations show that new parameters must be taken into account for hardness insurance at a high level of total dose.<>

Drain current transients for enhancement-mode partially-depleted SOl MOSFETs are investigated for the first time at temperatures up to 120°C, in weak and strong inversion. A straightforward analysis leads to the evaluation of the temperature dependence of the carrier lifetime. It is shown that transient effects vanish at high temperature.

The structure, operation principles and basic characteristics of SOI MOSFETs are evoked, before focusing on the degradation aspects. The hot-carrier injection into the front gate oxide and buried oxide is discussed as a function of silicon film thickness, transistor configuration (n- or p-channel, inversion- or accumulation-mode), and stressing bias. The special phenomena involved in ultra-thin, fully-depleted SIMOX MOSFETs are compared to those governing partially-depleted and bulk-equivalent transistors. It is demonstrated that the coupling between back-interface defects and front channel properties is a unique and very challenging degradation feature in SOI. The road map to reach an accurate electrical image of the degraded transistor, by accounting for coupling effects or by avoiding them, is described. Although the aging mechanisms and investigation methods are more sophisticated than in bulk Si, the degradation of SOI MOSFETs does not appear to impede on the development of high performance, low-voltage ULSI SOI circuits.

This paper concerns recent results on photon emission used for hot carriers degradation analysis. In a first part, we focus on quantitative light emission analysis on n- and p- channel MOSFETs for bulk and SOI technologies. On each device, the photon counts for different gate and drain voltages were measured and compared with the value of the substrate current. This shows that the measured value of the substrate current in SOI devices can be inaccurate. In a second part, we investigate light emission spectra for some specific biases. These measurements allow a clear comparison of the different technologies. Finally, a photon emission technique was used to analyse hot carrier degradation in circuits, the highest emissions are observed on NMOS transistors working at high frequencies, but emission have also been detected on PMOS transistors. A clear correlation with the working frequencies of the MOS has also been demonstrated.

We have studied the analog performance of the HSOI3-HD technology (industrialized by Thomson TCS, St. Egreve, France) up to a total dose of 25 Mrad of ionising radiation. Static parameters and their evolution have been extracted, and particular attention has been devoted to the noise. We found that most of the damage occurs in the first 12 Mrad, so the technology can find applications where tens of Mrad total doses are foreseen. P-channel transistors should be chosen as key elements in low noise ICs, with a maximum degradation of 18% in transconductance and better 1/f noise performance. A Generation-Recombination component in the noise spectra can be controlled through the body bias. We have studied the energy level of the trapping centers responsible for it and found that it is not modified by the irradiation

For several years, TCS has been involved in the transfer of epitaxial CMOS technology of microprocessors such as 68020 from Motorola and in the development of hardened Standard or ASIC products. The know-how which has bean acquired during these operations has led us to develop a rad tolerant process totally compatible in terms of design rules with standard CMOS process. Named HSOI4CB (CB for Compatible Bulk), this process is a 0.8 μm SOI CMOS with 2 levels of metallization. The use of the HSOI4CB technology allows us, without any specific effort on the design, to reach hardening levels compatible with space requirements up to more than 100 Krads

SOI transistors, operating in dynamic mode, have been fully investigated using dedicated test circuits. Indeed, specific circuits have been built in order to make, in-situ monitoring of electrical characteristics of n- and p-MOSFETs. We have demonstrated that physical mechanisms of the degradation, in partially depleted SOI devices, are comparable after static and dynamic stress. Indeed, back interface degradation analysis has revealed that, even after dynamic aging, p-MOSFETs are submitted to electron trapping while it is not the case for n-MOSFETs. The “quasi static” approach is not applicable in inverter-type circuit, and could be explained by successive injection of holes and electrons due to the specific bias waveform, leading to an enhancement of the degradation

The design and measurements of a 0.5 mW CMOS current mode amplifier in a SOI radiation hard technology are reported for a total dose of 20 Mrad(Si). It is designed for the fast readout of particle detectors in high energy physics experiments but could equally be applied to the readout of any capacitive sensor in a radiation environment. A pre-irradiation gain of 43.3 mV/4fC, rise time of 17 ns and Equivalent Noise Charge (ENC) of 1436e+78e/pF (1.97nV(Hz)/sup -1/2/) is achieved. Measurements are reported at 0, 10 Mrad(Si) and 20 Mrad(Si) with the evolution showing changes in peak voltage, rise time, parallel noise and series noise of -23%, 26%, 25% and 60% respectively after 20 Mrad(Si).

This paper focusses on the physical nature of the localized defects and on the comparison between thin and thick SIMOX devices. Thick MOSFETs, processed on epitaxial SIMOX films 1.2 μm thick, behave very similarly to bulk Si transistors. Thin MOSFET's were fabricated on 0.16 μm films and have characteristics corresponding to the transition between full and partial depletion (i.e weak interface coupling). Both N and P-channel transistors, with lengths of 0.5-1.4 μm, were stressed under various bias conditions. Several parameters (threshold voltage, transconductance and charge pumping current) were used to monitor the device degradation under static and alternating stresses

The analog performance of the Thomson HSOI3-HD technology has been measured up to a total dose of 12 Mrad(Si) of ionizing radiation (Co-60). The threshold voltage shift is -170 mV for p-channel and -20 mV for n-channel transistors. Transconductance degradation is respectively 4% and 17%. Noise has been measured in the 500 Hz-25 MHz bandwidth. In addition to the I/f and white noise, a generation-recombination contribution appears in the noise spectrum. This contribution is sensitive to the bias applied to the backgate and body electrodes. The white noise increase after irradiation is 16% for p-channel and 35% for n-channel transistors. p-channel transistors have very low I/f noise and are less sensitive to irradiation effects.

A direct comparison is made between SOI and bulk devices by fabricating "bulk like" and thin SIMOX film transistors. This work was conducted using single and alternating hot carrier injection such as to prepare the understanding of circuit degradation. Weak inversion characteristics as well as back interface trapping, after alternating injection, are studied for the first time. It was found that the basic mechanisms are similar for the two studied technologies. However, several differences are observed during alternating injection: (i) transconductance recovery in thin film n-channel MOSFETs and (ii) a recovery of the off-state current in thin film p-channel MOSFETs.<>

A new rad-hard technology suitable for high energy physics electronics is currently under development. This technology uses a SOI substrate with a thick silicon film. It includes CMOS, CJFET and complementary vertical bipolar transistors with a potential multi-Mrad hardness for all these devices. These devices enable the design of both analog and digital functions. CMOS together with bipolar transistors will constitute a BiCMOS technology which will be useful to build high speed architectures. JFETs, which have an intrinsically high hardness behaviour and low noise, should allow the design of very radiation-hard low-noise front-end electronics and are also good candidates for cryogenic applications.

The degradations of the SIMOX buried oxide after either front channel stress in p-MOSFETs or back channel stress in n-MOSFETs are analyzed as a function of drain bias and correlated. It is found that this damage may be alleviated and the device lifetime extended over 10 years by scaling the drain bias below 3V.

Radiation hardened SOI-CMOS is a possible candidate technology for mixed analog-digital signal processing electronics in experiments at the future high luminosity hadron colliders. In view of this application, we have studied the analog parameters of transistors realized in the Thomson TMS HSOI3-HD technology before and after exposure to total doses similar to those expected in the CERN Large Hadron Collider LHC. The devices have been irradiated up to 10 Mrad with Co-60 and 3 . 10(14) neutrons/cm2. The changes in the threshold voltage V(th) of front and back gates, leakage current and transconductance are studied. Subthreshold slope and charge pumping techniques have been used to estimate the interface state formation. Noise measurements in the 0.1kHz-3MHz bandwidth have been performed. The noise is comparable to that of a bulk CMOS process. Post irradiation effects have been regularly monitored and threshold voltage rebound for n-channel transistors is observed.

An 8 bit 20 MHz flash ADC using a radiation hardened SOI process is presented. The circuit is capable of operating at up to 20 MHz, even after a total dose exposure of 100 MRad (SiO2) (10 Kev X-ray).

CMOS silicon on insulator technology has shown its ability to process hardened components which remain functional after irradiation with a total dose of several tens of Megarads. New tests on elementary transistors and 29101 microprocessor have been made at doses up to 100 Mrad(Si02) and above. Results of irradiation at these total doses are presented for different biases, together with the post-irradiation behaviour of the components. A11 the observations show that new parameters must be taken into account for hardness insurance at a high level of total dose. micron and the active Silicon thickness is 0.15 micron. The gate electrode is made from N+ polysilicon covered with TaSi2. The SIMOX substrate (Synthesis by IM lantation of Oxygen) is implanted at a dose of 1.8 10 f8 cm-2 02+ and annealed at 1320°C for 6 hours.

An analytical model and experimental results are proposed to account for the floating body effects in silicon-on-insulator (SOI) MOSFETs. It is shown both theoretically and experimentally that an SOI MOSFET may exhibit simultaneously a negative conductance and a negative transconductance. The evolution of these effects under an X-ray exposure is studied and described in detail.< >

A model is proposed to describe the variation of the transaconductance in fully-depleted silicon on insulator MOSFETs as a function of the front/back gate biases, channel length and series resistances. The influence of series resistances on the static characteristics of short-channel transistors depends on the region of operation, via the front and back gate voltages, and is a maximum when both interfaces are inverted. Simple analytical expressions explain the gradual deformation of the transconductance curve and the lowering of the transconductance peak with increasing series resistances. The model is experimentally verified by associating external resistors to the transistor. It is shown that a major consequence of X-ray irradiations in short-channel SIMOX MOSFETs is the trapping of positive charges in the buried oxide, which causes activation of interface coupling effects and enhanced influence of series resistances.

An analytical model is proposed to account for the floating body effects in silicon on insulator MOSFET's. It enables a quantitative description of the hysteresis effects in the static characteristics and explains the correlation between the conductance and transconductance. Experimental data illustrate the occurrence of the negative conductance/transconductance and suggest that a critical phenomenon comparable to a second order phase transition takes place.