For several years, TCS has been involved in the transfer of epitaxial CMOS technology of microprocessors such as 68020 from Motorola and in the development of hardened Standard or ASIC products. The know-how which has bean acquired during these operations has led us to develop a rad tolerant process totally compatible in terms of design rules with standard CMOS process. Named HSOI4CB (CB for Compatible Bulk), this process is a 0.8 μm SOI CMOS with 2 levels of metallization. The use of the HSOI4CB technology allows us, without any specific effort on the design, to reach hardening levels compatible with space requirements up to more than 100 Krads

THOMSON-CSF Semiconducteurs Specifiques (TCS) and the CEA-LETI have developed a 0.8 mu m SOI bulk compatible process (HSOI4CB) for space and battle field applications. The main motivation for this process is to allow the transfer of already existing bulk circuits onto SOI with reduced redesign effort and performances degradation. In this paper, SOI process (HSOI4CB) and the 68020 transfer are summarized, including the most significant characteristics of the resulting product (68T020), in terms of Single Event Upset (SEU) and Single Event Latch-up (SEL). For the same revision version, the 68T020 comparisons with bulk or epitaxial 68020 processes are given.

The authors review the complete automated implementation of the IEEE P1149.1 boundary scan standard proposed in the CSAM ASIC compiled technology-independent library based on the GDT/GENESIL silicon compiler environments. The advantage of this compiled approach is to provide a flexible set of boundary scan cells, including pads and test access port (TAP) controllers. The boundary scan register is automatically created when compiling the pad ring and different parameterized function complexities allow easily the dedication of the TAP controller to any application. The user-defined elements implementation is also supported, especially by means of logic synthesis, and a test vector generation tool allows one to automatically generate the serial boundary scan test vectors from the parallel test vectors defined for the manufacturing test of the circuit. The cost of boundary scan integration has shown to be reasonable in the manufactured chips.<>

This paper reviews the design carried out to implement the IEEE P1149.1 boundary scan standard in the TSBC3 compiled portable library based on the GDT®/GENESIL® tools. The advantage of this compiled approach is to provide a flexible set of boundary scan cells, including pads and Test Access Port (TAP) controllers. The boundary scan register is automatically assembled while creating the pad ring and different parameterized function complexities allow to easily dedicate the TAP controller to any application. The cost of boundary scan integration has shown to be reasonnable in comparison with the ease of board testing.