Hole electrical transport in a p-doped nanochannel defined between two L-shape etched trenches made on a silicon-on-insulator substrate is investigated using a TCAD-Medici simulator. We study the impact of the etched trenches' geometry and dielectric filling materials on the current-voltage characteristics of the device. Carrier accumulation on frontiers defined by the trenches causes a modulation of the hole density inside the conduction channel as the bias voltage varies and this gives rise to a diode-like characteristic. For a 1.2 mu m-long channel, plots of the electric field distribution show that a nonlinear transport regime is reached at a moderate reverse and forward bias of +/- 2 V. Plots of the carrier velocity along the conduction channel show that holes remain hot for a few hundreds of nm outside the nanometre-wide channel, at a bias of +/- 10 V. Filling the etched trenches with a high-kappa dielectric material gives rise to a lower threshold voltage, V-th. A similar decrease of Vth is also achieved by reducing the longitudinal and/or the transverse trench width. Our simulation results provide useful design guidelines for future integrated self-switching-diode-based circuits.

Using the TCAD-Medici simulator, we have studied the electrical transport in several lateral field effect devices, communely called Self-switching devices (SSDs) essentially based on SOI. This new type of nanometer-scale, rectifying devices, is realised by tailoring the boundary of a narrow semiconductor channel to break its longitudinal symmetry [1]. Our first goal was to adjust our experimental data measured at 300K with Medici simulated ones obtained in the same conditions. As shown on figure 01, we obtain an excelllent agreement between the simulated and the experimental current-voltage characteristics measured at room temperature on a ptype SOI based SSD shown in the inset of figure 01. The width of the channel and the etched grooves are 230nm and 200nm respectively. More details about the fabrication process and the experimental results are reported in [2]. The simulated results take into account the presence of a uniform surface charge density [3], Qss, between the insulating etched grooves and the semiconductor [4] and is deduced by fitting experimental data with medici I-V curves. The best agreement is obtained for Qss = 3.4×10 cm. The adjustement of the experimental data shown in figure 01 requires to take into account the existance of a non-negligible leakage current through the etched grooves and a series resistance due to the current leads. These results suggest that in order to prevent the leakage current and the effect of parasitic resistances to optimize the electrical performance of the device, it is preferable to increase the width of the etched grooves far enough from the active device and of course to decrease the length of the current leads. We have also studied the effect of the small size of the device on the hole transport inside the channel of the SSD. In fact, even an applied voltage as small as 1V induces sufficently high electric field in the nanochannel to be in presence of hot carriers and nonlinear transport. This fact is proven by the simulation results which shows that both the hole density and velocity in the channel vary in a nontrivial manner versus the applied voltage du to the nonsymetrical geometry of the studied device. In particular, we show that the breakdown in reverse appears more gradually than in a pn junction. In figure 02, we represent the variation of the hole velocity all along the simulated device. The channel is situated between the abscissas 0μm and 1.2 μm. We can see that the value of the hole velocity drops quickly under the limit value of 3×10 cm/s (the approximate value beyond of which the carriers are considered hot carriers) even if we apply voltage biases up to +10V. For reverse biases up to -10V, the hot holes need to go about 300nm away from the exit of the channel to relax their energy. These results illustrate the importance to take into account the distance needed for hot holes to relax in the eventuality of the integration of such devices for circuit applications.

Self-switching devices (SSDs) are new nano-scale field effect active components. In the present work, these devices are made in silicon-on-insulator (SOI) technology and operate at room temperature. We investigate their current–voltage (I–V) characteristics which show a diode-like behaviour due to electrostatic effects. Thermal activation measurements are presented and discussed. We also present simulations to gain better understanding of device physics and also to optimize the critical parameters of the fabrication process.

The work on SOI shows that SSDs can be compatible with advanced CMOS on SOI technologies, which greatly enhances the possibilities to practically use SSDs. One of the most significant advantages of SSDs is the remarkably simple process requiring only to create trenches in a semiconductor film. By combining a few SSDs, simple logic gates can be fabricated also in one lithography step (Song, 2003). The SSDs can also be used as memory cells working at room temperature as demonstrated in ref. 6. Furthermore, one can form a lateral gate on one side of the channel thus making a self-switching transistor (SST) opening more possibilities for applications. These various devices are under fabrication on SOI and characterisation in our group. We believe that that SSDs on SOI may provide remarkable simplicity and flexibility in circuit design and fabrication

The problem of high input impedance of nanoscaled devices is analyzed for the case of a Y-Branch Junction. An electrical nonlinear model of YBJs validated on measured data is used to show influence of source impedance on HF to DC detection performance in YBJ. An impedance matching network is proposed and is proven to increase the detection sensitivity. Multiple 2DEG channels material used to fabricate parallel YBJ's stacked on one another is also proposed as an alternative solution to mismatch problem. It is shown that using multiple 2DEG the input impedance and reflection coefficient can be decreased but at the price of decrease in sensitivity

A double Y-branch ballistic junction is proposed for rectification of signals up to 94 GHz. A nonlinear model is developed to predict the frequency dependence of its RF to DC conversion performances, and agrees very well with experiment. The model shows the importance of minimizing extrinsic parasitics when designing HF ballistic nanodevices.

Room-temperature dc and broad-band high-frequency (HF) to dc conversion measurements of a double Y-branch junction (YBJ) are presented and discussed. Nonlinear dc characteristics of the devices at room temperature are observed and HF to dc conversion up to 40 GHz at room temperature is presented. The HF to dc conversion efficiency degradation is found to be partly due to losses in interconnects feeding the device. A small-signal equivalent circuit of the YBJ is proposed in order to verify the frequency dependence of intrinsic elements.

We report on DC and broadband HF to DC conversion measurements of a Double Y-branch junction. Nonlinear DC characteristics of the devices are observed and HF to DC conversion up to 50GHz at 77K and at room temperature is presented. The HF to DC conversion efficiency degradation at high frequencies is found to be partly due to losses in interconnects feeding the device.

A detailed analysis of nonlinear effects-electron switching and rectification, in InAlAs/InGaAs based Y-branch junction (YBJ) devices is presented to investigate the potential of YBJ for high frequency applications at 300K. Results based on semi-classical simulations yield good qualitative agreement with measurements and previously reported theoretical and experimental results. The nonlinear parabolic behaviour of our device is attributed to device geometry and space charge effects. RF analysis shows that the YBJ has tremendous intrinsic potential to function as a frequency doubler and microwave rectifier when operated in the parabolic regime. The present analysis serves as a tool to optimize the bias conditions for RF measurements and to estimate the effect of interconnects and parasitic elements on the RF performance of real devices.

The phase coherence time tau(phi) and spin-orbit coupling time tau(so) are measured in a bismuth quasiballistic nanocavity and in bismuth thin films using weak antilocalization and universal conductance fluctuations. The cavity is found to be zero dimensional for phase-coherent processes at low temperature. Weak antilocalization seems weakly affected by this drastic reduction of dimensionality. The temperature dependence of tau(phi) is similar in both types of samples, qualitatively consistent with low-energy transfer two-dimensional electron-electron interaction effects as the dominant dephasing mechanism. Strikingly, tau(phi) in the dot is found to be an order-of-magnitude smaller than in the film, and orders-of-magnitude smaller than the theoretical prediction.

We report on the observation of weak antilocalization and universal conductance fluctuations in the magnetoconductance of an open quasi-ballistic bismuth nano-cavity. The electron decoherence length is comparable to sample dimensions at low temperature, while the spin–orbit coupling length is smaller. The temperature dependence of both the conductance and the dephasing length are consistent with two-dimensional electron–electron interactions being the dominant decoherence process.