High-electron-mobility transistors (HEMTs) based on gallium nitride (GaN) grown on silicon substrates are emerging as a promising solution for high-performance and cost-effective power electronics. However, their widespread adoption is hindered by a critical limitation: the vertical breakdown voltage, typically capped at around 900 V, due to leakage current and destructive breakdown occurring beneath the drain contact. In this work, we introduce a novel device architecture that integrates a thin p-type GaN layer inserted below the buffer layer. This additional layer enables a more favorable redistribution of the electric field, effectively suppressing undesirable vertical destructive breakdown of the device. This innovative idea is validated through both TCAD simulations and experimental device fabrication. A vertical breakdown voltage of 530 V was achieved for a GaN buffer layer thickness reduced to 1.5 mu m, representing state-of-the-art performance for GaN-on-silicon devices within this thickness range. Furthermore, the occurrence of an avalanche is of critical importance, as it ensures that the observed breakdown remains nondestructive, preventing catastrophic failure and enhancing the overall robustness of the device. This new idea marks a significant step forward in the development of reliable and economically viable GaN-on-silicon power devices, with substantial potential for impact on electric mobility, renewable energy conversion, and data center power infrastructure.

This work presents a temperature-dependent micro-Raman spectroscopy study (300-573 K) of homoepitaxial n-type GaN layers with different Si doping levels ranging from 1015 to a few 1018 cm-3, where the analysis of different vibrational modes enables simultaneous extraction of structural and electronic properties. The evolution of the E2(high) mode and the associated phonon correlation length with doping and temperature reveal progressive lattice disorder, allowing static disorder related to dopant incorporation to be distinguished from dynamic disorder arising from phonon interactions. In parallel, the A1(LO) mode highlights the Fano interaction between the discrete phonon and the electron continuum, where the asymmetry parameter provides access to the Fermi level EF position. At 300 K, the energy separation between the conduction band and EF decreases from ∼0.19 eV for the lightly doped sample to ∼0.03 eV for the heavily doped sample. At 573 K, this distance increases to ∼0.43 eV and ∼0.08 eV, respectively, reflecting the temperature-dependent shift of the chemical potential. These results confirm both efficient dopant activation and the transition toward quasi-degenerate behavior at high carrier concentrations. Finally, analysis of A1(LO) phonon-plasmon coupling within the LPP model allows the determination of carrier mobility as a function of doping and temperature: at 300 K, the mobility decreases from 916 cm2/V·s in lightly doped samples to 355 cm2/V·s in heavily doped layers, with further reductions at elevated temperatures due to thermally activated scattering and carrier redistribution. These results demonstrate that Raman spectroscopy is a powerful nondestructive tool to simultaneously assess electronic transport properties and crystalline disorder in vertical GaN-based power electronics.

In this work, using micro-Raman spectroscopy mapping, we propose a methodology to separate the stress effect from the n-doping effect on A(1) (LO) and E-2(H) GaN phonon modes frequency for low n-doped (<1017 cm-3) GaN layers grown on various substrates (GaN, sapphire, and silicon). This methodology shows a linear relation between the two phonon modes, in which the slope corresponds to GaN biaxial stress coefficients ratio K-A1(B) ((LO))/K-E(B)H 2 and is 0.76 6 0.01. Our value may act as a useful guideline for selecting or refining K-E(B)H 2 and K-A1(B)(LO) values. Samples that are mainly biaxially stressed show good agreement with the linear relation independently of the substrate. As for GaN/GaN samples, the change of slope indicates that layers are predominantly under dislocation-induced stress. However, independently of the substrate, the y-intercept increases with the n-carrier concentration, which provides a qualitive estimation of the net doping.

This paper details a method for the characterization and modeling of GaN HEMT transistors on silicon substrate, with a focus on providing a reproducible workflow, step-by-step characterization procedure, identification scripts for the model parameters and sample data. Static (Id(Vgs),Id(Vds)) and dynamic (C(Vds)) measurements are conducted to identify key device parameters across a wide current range, from nanoamperes to several amperes. Based on these measurements, a modeling approach inspired by existing literature is implemented using Matlab, enabling the generation of a robust LTspice compatible models. The constructed models are validated through double-pulse tests on two distinct GaN devices, demonstrating good agreement between simulation and experimental results. This work offers a turnkey solution for researchers and engineers seeking GaN HEMT’s models efficiently.

We demonstrate the fabrication of air gaps in a PECVD SiN interlayer through lateral recess by employing two consecutive plasma etch steps on an AlN/SiN/Al2O3 stack. This approach enables the preservation of sub-100 nm openings in Al2O3, offering a potential optimization for the GaN-HEMT gate stack in RF applications while retaining low gate foot dimensions. A low-power, SF6-based plasma etch is introduced, and time-dependent etch profiles reveal the formation of a skirt-like profile. The process exhibits excellent selectivity between SiN and Al2O3 etch rates. Furthermore, low-power SF6 plasma produces a small self-bias voltage, and surface fluorine contamination which can subsequently be eliminated by annealing.

The forward and reverse current transport mechanisms, temperature dependence of Schottky barrier height (SBH) and ideality factor, barrier inhomogeneity analysis, and trap parameters for Schottky barrier diodes (SBDs) fabricated on 4H-SiC, GaN-on-GaN and AlGaN/GaN epitaxial substrates are reported. High SBH is identified for Ni/4H-SiC (1.31 eV) and Ti/4H-SiC (1.18 eV) SBDs with a low leakage current density of <10(-8) A cm(-2) at -200 V. Thermally stimulated capacitance detects the well-known Z(1/2) electron trap at E-C-0.65 eV in both 4H-SiC SBDs, while an additional deep-level trap at E-C-1.13 eV is found only in Ni/4H-SiC SBDs. The vertical Ni/GaN SBD exhibits a promising SBH of 0.83 eV, and two electron traps at E-C-0.18 eV and E-C-0.56 eV are identified from deep-level transient Fourier spectroscopy. A peculiar two-diode model behavior is detected at metal/GaN/AlGaN/GaN interface of high-electron mobility transistor (HEMT); the first diode (SBH-1 of 1.15 eV) exists at the standard Metal/GaN Schottky junction, whereas the second diode (SBH-2 of 0.72 eV) forms due to the energy difference between the AlGaN conduction band and the heterojunction Fermi level. The compensational Fe-doping-related buffer traps at E-C-0.5 eV and E-C-0.6 eV are determined in the AlGaN/GaN HEMT, through the drain current transient spectroscopy experiments.

Designing a monolithic circuit around a GaN/Si High electron mobility power transistor requires accurate characterization and device modeling. The characterization aims to provide adequate parameters to the transistor model. In particular, the characterization protocol presented in this paper enables to capture a wide range of current, from very low currents (a few hundred picoamperes to a few nanoamperes) when the transistor is off (sub-threshold), to high currents (several hundred milliamperes to a few amperes) when the transistor is on. A special care is given to detecting any drift in the component characteristics which may be caused by the characterization step. A modeling procedure is also presented, to build a SPICE parametric model of the transistor. An $R^{2}$ criterion is used to validate the resulting models.

This paper introduces a novel technology for the monolithic integration of GaN-based vertical and lateral devices. This approach is groundbreaking as it facilitates the drive of high-power GaN vertical switching devices through lateral GaN HEMTs with minimal losses and enhanced stability. A significant challenge in this technology is ensuring electrical isolation between the two types of devices. We propose a new isolation method designed to prevent any degradation of the lateral transistor’s performance. Specifically, high voltage applied to the drain of the vertical GaN power FinFET can adversely affect the lateral GaN HEMT’s performance, leading to a shift in the threshold voltage and potentially compromising device stability and driver performance. To address this issue, we introduce a highly doped n+ GaN layer positioned between the epitaxial layers of the two devices. This approach is validated using the TCAD-Sentaurus simulator, demonstrating that the n+ GaN layer effectively blocks the vertical electric field and prevents any depletion or enhancement of the 2D electron gas (2DEG) in the lateral GaN HEMT. To our knowledge, this represents the first publication of such an innovative isolation strategy between vertical and lateral GaN devices.

Controlling properties of GaN/dielectric interfaces is crucial for determining the characteristics of MOS-HEMT devices and their stability. Interface properties are largely affected by the techniques and specific conditions of dielectric deposition. In this work, a Taguchi design of experiment was applied to study the effect of plasma parameters during deposition of SiOx by PECVD for passivation of n-GaN. SiOx/GaN MIS capacitors were fabricated and characterized by capacitance measurement at a high probing frequency of 1 MHz. The interface states density, hysteresis and flatband voltage were analyzed and modeled in relation with the flow of SiH4, plasma power, chamber pressure and temperature. Excellent fits could be obtained on a single model including linear terms for all studied parameters and quadratic terms for the flow of SiH4 and temperature. We show that it is possible to obtain some control of the flatband voltage while maintaining a good interface quality. Positive flatband voltages are potentially of interest to enable normally-off operation for MOS-HEMTs and this could be obtained mainly by using a high SiH4/N2O ratio. To the contrary, negative flatband voltage values often ensure the most stable operation of MOS-HEMTs and this was achieved with a low SiH4/N2O and high plasma power. MIS capacitors with near-zero flatband voltage were also obtained with low SiH4/N2O ratio and low plasma power. Hysteresis and interface states density in relation with deposition plasma conditions are also analyzed in order to offer the best trade-offs depending on the end applications of MOS-GaN devices. By demonstrating the great impact of plasma conditions during dielectric deposition on electronic properties of MIS devices, we show that the process of gate insulation can be optimized to simultaneously control the density of defects and fixed charge at the interface.

In this work, the physical and the electrical properties of vertical GaN Schottky diodes were investigated. Cathodo-luminescence (CL), micro-Raman spectroscopy, SIMS, and current-voltage (I-V) measurements were performed to better understand the effects of physical parameters, for example structural defects and doping level inhomogeneity, on the diode electrical performances. Evidence of dislocations in the diode epilayer was spotted thanks to the CL measurements. Then, using 2D mappings of the E-2(h) and A(1) (LO) Raman modes, dislocations and other peculiar structural defects were observed. The I-V measurements of the diodes revealed a significant increase in the leakage current with applied reverse bias up to 200 V. The combination of physical and electrical characterization methods indicated that the electrical leakage in the reverse biased diodes seems more correlated with short range non-uniformities of the effective doping than with strain fluctuation induced by dislocations.

During the fabrication of metal oxide semiconductor high electron mobility transistor based on AlGaN/GaN heterostructure, gate patterning is recognized as the most critical step that can lead to electrical degradation of the transistor. In this work, we performed the SiN cap layer plasma etching processes by two fluorine-based plasma processes (SF6/Ar and CHF3/CF4/Ar) with low (≈15 eV) and high (≈260 eV) ion energies. Moreover, we investigate the postetching treatment using a KOH solution in order to restore the quality of the AlGaN barrier surface after etching. The objective of this article is to evaluate the AlGaN barrier surface damage after the listed plasma etching processes and postetching strategies by using quasi-in situ angle-resolved x-ray photoelectron spectroscopy, transmission electron microscopy, and atomic force microscope. Accordingly, it is found that both high ion energy plasma processes lead to a significant stoichiometric change and modification of the AlGaN barrier layer into a 1.5 nm F-rich AlGaNFx subsurface reactive layer. The decrease in ionic energy leads to a decrease in the SiN etch rate and a significant improvement in the SiN/AlGaN etch selectivity (which becomes infinite) for both plasma chemistries. Moreover, the decrease in ion energy decreases the depth of the modification (about 0.5 nm) and reduces the stochiometric change of the AlGaN barrier layer. However, both low and high ion energy SF6/Ar plasma lead to 0.8 eV Fermi level shift toward the valence band. Furthermore, the KOH postetching treatment demonstrates complete and effective removal of the AlGaNFx subsurface reactive layer and restoration of the surface properties of the AlGaN layer. However, this removal leads to AlGaN recesses that are correlated to the thickness of the reactive layer formed during the etching.

The paper explores the Deep Level Transient Fourier Spectroscopy (DLTFS) capabilities in characterizing electrically active traps in vertical GaN-on-GaN Schottky barrier diodes (SBDs). The capacitance-DLTFS (C-DLTFS) experiments reveal a prominent electron trap T2 at E-C - 0.56 eV with a density (N-T2) of 8 x 10(14) cm(-3) and a weak presence of another trap at E-C - 0.18 eV (T1) with N-T1 = 3.8 x 10(13) cm(-3) in the SBDs. The C-DLTFS acquired with two emission transients (T-E = 20.48 ms and 2.048 s) has resulted in identical trap signatures for T1 and T2. Due to the high N-T, the trap T2 at E-C - 0.56 eV is identified from the current-DLTFS (I-DLTFS) and thermally stimulated capacitance (TSCAP) measurements. Especially the TSCAP results indicate the carrier freeze-out temperature (T < 75 K) in the GaN material. Furthermore, the carrier emission kinetics of the trap T2 is evaluated by performing isothermal transient spectroscopy at a stabilized temperature. The capture time constant of T2 is estimated from the isothermal transients attained with shorter trap-filling pulse widths (<100 ns).

We report on the fabrication of an enhancement mode p-GaN/AlN/GaN high electron mobility transistor with selective area sublimation under vacuum of the p-GaN cap layer. The GaN evaporation selectivity is demonstrated on the thin 2 nm AlN barrier layer. Furthermore, the regrowth of AlGaN is a major key to increase the maximum drain current in the transistors and enables the co-integration with depletion mode devices.

— This work presents an innovative technology where GaN-based vertical and lateral devices are monolithically integrated. Indeed, this technology will enable to drive high-power switching devices (vertical GaN power FinFETs) using lateral GaN HEMTs with minimum losses and high stability. The main challenge of this technology is the electrical isolation between these two devices. In this paper, a new isolation approach is presented to avoid any degradation of the lateral transistor performance. In fact, the high voltage applied at the drain of the vertical GaN power FinFET can drastically affect the drain current of the lateral GaN HEMT. To overcome this problem, a highly doped n + GaN layer is inserted between the epi-layers of these two devices. TCAD-Sentaurus simulator is used to validate this new approach. Indeed, this highly n-doped GaN layer is blocking the vertical high electrical field and preventing any depletion of the 2D gas of the lateral GaN HEMT. To the best of our knowledge, it is the first time where the vertical and lateral GaN devices are integrated within the same technology.

The impact of Cubic Silicon Carbide (3C-SiC) transition layer on breakdown voltage and frequency performance of GaN high electron mobility transistors is investigated. A combination of distinct material and device characterizations techniques, including Raman spectroscopy, coplanar waveguides, electrical measurements, and Technology Computer-Aided Design (TCAD) simulations, are adopted to inspect the role of the 3C-SiC interlayer. Raman spectra reveal a good quality of the 3C-SiC layer, similar to the mono-crystalline 3C-SiC spectra. A relatively low transmission loss of ∼0.16 dB/mm at 40 GHz is measured for the device with 3C-SiC layer, rather than 2.1 dB/mm for the device without 3C-SiC. In addition, a soft breakdown voltage around 1530 V at 1 μA/mm is achieved, which is three times larger compared with that of the conventional device. The failure mechanism, related to carrier injection at the nucleation layer, is not observed in the structure with the 3C-SiC layer. Instead, TCAD simulations disclose a substantial improvement of the buffer/substrate interface through the suppression of an interface current path.

Two low-damage plasma etching processes have been investigated to evaluate their impact on the integrity of the AlGaN layer during the SiN gate opening process of Metal Insulator Semiconductor High Electron Mobility Transistors (MIS-HEMT). We show that the low ion energy fluorocarbon plasma presents an infinite SiN/AlGaN etch selectivity despite significant surface modifications. In contrast, the smart etch process, that alternates H 2 plasma-based surface modification with chemical removal of the modified surface, preserves the surface of AlGaN. However it can lead to AlGaN recess due to over-implantation during the H 2 plasma step. Finally, we show that a KOH post etchi treatment removes plasma-induced damages. Therefore, combining the smart etch process with a KOH post etch treatment offers an interesting solution for SiN patterning over AlGaN with minimized surface modification and restored AlGaN surface quality.

This paper reports comprehensive characterization of vertical GaN-on-GaN Schottky barrier diodes (SBDs) fabricated on free-standing GaN substrates. The GaN active layer properties are evaluated by atomic force microscopy (AFM), secondary-ion mass spectrometry (SIMS), micro-Raman spectroscopy, cathodoluminescence (CL), and deep-level transient Fourier spectroscopy (DLTFS). The GaN SBDs exhibit near-unity ideality factor (n = 1.1), promising Schottky barrier height (SBH) of Phi(B) = 0.82 eV, low turn-on voltage similar to 0.56 V, leakage current density of J(R) < 5.5 x 10(-6) Acm(-2) at -100 V, breakdown voltage V-BR < -200 V, and less interface state density (N-SS < 5 x 10(12) eV(-1) cm(-2)) at the Ni/GaN Schottky contact. The forward and reverse current transport mechanisms of the SBD are identified by fitting analysis of measured J-V. Weak temperature dependence of Phi(B) and n is detected from I-V-T measurements. Similar traps at E-C - 0.18 eV and E-C - 0.56 are identified in the various SBDs from DLTFS, signifying that these traps are omnipresent defects in the epilayer.