Self-aligned 0.55×3.5 μm 2 emitter InP/GaAsSb/InP double heterojunction bipolar transistors demonstrating an f t of 310 GHz and an f max of 480 GHz are reported. Common-emitter current gain of 24, together with a breakdown voltage of 4.6 V, is measured. The devices were fabricated with a triple-mesa process and easily fabricated with a new base isolation μ-airbridge design which, moreover, significantly reduced the base-collector capacitance C BC .

In this paper, a fully passivated InP/GaAsSb/InP DHBT on InP substrate with excellent DC and RF performance is developed. The epi-layers are grown by the MOCVD technique, with a base layer of 25nm and a collector layer of 130nm. The emitter width of the transistor is 0.35µm and the base contact is 0.3µm wide. The base and emitter contacts present an excellent contact resistivity. The current gain of the 0.35x5µm2 transistor is equal to 21 and the breakdown voltage is equal to 4V. The current gain cut-off frequency and the unilateral gain cut-off frequency are over 300 GHz and 380 GHz respectively. The transistor is fabricated in an industrial environment at OMMIC foundry.

In this paper, a fully passivated InP/GaAsSb/InP DHBT on InP substrate with excellent DC and RF performance is developed. The epi-layers are grown by the MOCVD technique, with a base layer of 25 nm and a collector layer of 130 nm. The emitter width of the transistor is 0.35 μm and the base contact is 0.3 μm wide. The base and emitter contacts present an excellent contact resistivity. The current gain of the 0.35×5μm2 transistor is equal to 21 and the breakdown voltage is equal to 4 V. The current gain cut-off frequency and the unilateral gain cut-off frequency are over 300 GHz and 380 GHz respectively. The transistor is fabricated in an industrial environment at OMMIC foundry.

A high DC and RF performance, fully passivated, true enhancement-mode 100 nm MHEMT is demonstrated. This transistor is a good candidate for high performance low noise and low power consumption applications

A high DC and RF performance, fully passivated, true Enhancement-mode 100nm MHEMT is demonstrated. This transistor is a good candidate for high performance low noise and low power consumption applications. The dynamic performance of a HEMT device directly depends on the growth structure and the manufacturing technology. Compared with other types of HEMT’s, the InAlAs/InGaAs/InAlAs HEMT is a unique candidate for high-speed low noise circuits due to its excellent electrical performances [1] but unfortunately suffers from poor static characteristics and dynamic performance limitations at short gate lengths. This paper is focused on another type of HEMT family, which is the Enhancement mode HEMTs. To obtain a high static and dynamic performance E-mode HEMT (E=Enhancement) usable for mixed-mode analogue-digital circuits, the optimization of both the epitaxial structure and the process has been done. The principal target of this study is the realization of an E-HEMT transistor with a large gate voltage swing, a really positive pinch-off voltage and good dynamic performance. A trade-off between these parameters should be found. The gate voltage swing and the pinch-off voltage are defined at gate current and drain current both equal to 1 mA/mm which gives a tight specification for gate leakage current with the required epitaxial structure. Besides the above mentioned constraints, a true E-HEMT should have a Schottky barrier height (SBH) bigger than the conduction band offset in between the barrier layer and the channel ( Ec), which is difficult to obtain for a lattice matched InP-HEMT where the SBH is about 0.58-0.7 eV and Ec~ 0.52 eV [2]. Moreover, the small SBH of the In0.52Al0.48As drastically affects the gate leakage current and consequently the gate voltage swing of the device. In this paper we present the results of an In0.4Al0.6As/In0.4Ga0.6As/In0.4Al0.6As EMHEMT with an SBH in excess of 1 eV and a Ec~0.65 eV. Using such a structure it is possible to achieve a positive pinch-off voltage above 0.2V and a wide gate voltage swing, which is not the case for an InPHEMT where we cannot increase the gate voltage over 0.5 V while keeping Ig<1mA/mm. S.I. GaAs Substrate nid In0,40Al0.60As -doping InxAl1-x As Graded M-Buffer n++ In0.40Ga0.6As