This paper reports on the enhanced piezoresistive effect in p-type <;110> silicon nanowires, fabricated using a top down approach. The silicon nanowire width is varied from 100 to 500nm with thickness of 200 nm and length of 9μm. It is found that the piezoresistive effect increases when the nanowire width is reduced below 350 nm. Compared with micrometre sized piezoresistors, silicon nanowires have produced up to 50% enhancement. Silicon nanowire with cross-section of (100 × 200 nm) with doping concentration of 3.2 × 10 18 cm -3 has produced a gauge factor of 150. The extracted gauge factors are compared with other silicon nanowire experimental publications. The enhancement in piezoresistive effect by employing non-suspended silicon nanowire is beneficial for new MEMS pressure sensors with medium doping concentrations.

This paper investigates the characteristics of silicon piezoresistors with various dopin g concentrations and Length/Width dimensions at micro level. The silicon piezoresistors have been produced by conventional fabrication methods. The measurements are conducted on silicon test chips where p-type resistors are fabricated on n type (100) silicon substrates along the <110> direction. A fou r point bending setup has been designed and fabricated for characterizing the piezoresistor sets. The f our point bending setup is used to apply uniform uniaxi al stress along the <110> direction. This experimental result demonstrates a good linear relationship between resistance change and stress applied. The effect of doping concentration on temperature sensitivity is also investigated.

Applications involving transfer of germanium layers to silicon-based substrates often require a process involving a restricted thermal budget. The use of relatively low temperatures has a major advantage in reducing stresses when thermal splitting of implanted germanium wafers bonded to silicon-based substrates is used to create germanium-on-oxide (GeOI) layers. The present study investigates the phenomenon of blistering of hydrogen and helium co-implanted germanium over the temperature range 250–400°C, optical microscopy being used to detect the initial appearance of the blisters. Results showed that plots of Ln(time) vs. blister initiation temperature consisted of several straight-line regions yielding an activation energy for each region. The plots showed similarities to those observed in previous work with silicon co-implanted and annealed under similar conditions. At temperatures below the blister initiation temperature, transmission electron microscopy (TEM), revealed the presence of spherical bubbles at a depth below the surface estimated to be approximately that of the hydrogen implant projected range. GeOI layers were produced by thermal splitting of co-implanted germanium wafers bonded to oxide-coated silicon substrates wafers at a temperature of 300°C. The RMS roughness of the split germanium surface measured by atomic force microscopy (AFM) was about 11nm averaged over the wafer surface. In addition there were isolated and randomly distributed regions of 27nm roughness covering about 20% of the total surface area of the wafer.

This paper explores the potential of germanium on sapphire (GeOS) wafers as a universal substrate for System on a Chip (SOC), mm wave integrated circuits (MMICs) and optical imagers. Ge has a lattice constant close to that of GaAs enabling epitaxial growth. Ge , GaAs and sapphire have relatively close temperature coefficients of expansion (TCE), enabling them to be combined without stress problems. Sapphire is transparent over the range 0.17 to 5.5 μm and has a very low loss tangent (α) for frequencies up to 72 GHz. Ge bonding to sapphire substrates has been investigated with regard to micro-voids and electrical quality of the Ge back interface. The advantages of a sapphire substrate for integrated inductors, coplanar waveguides and crosstalk suppression are also highlighted. MOS transistors have been fabricated on GeOS substrates, produced by the Smart-cut process, to illustrate the compatibility of the substrate with device processing.

Hafnium oxide films have been deposited at 250 °C on silicon and germanium substrates by atomic layer deposition (ALD), using tetrakis-ethylmethylamino hafnium (TEMAH) and water vapour as precursors in a modified Oxford Instruments PECVD system. Self-limiting monolayer growth has been verified, characterised by a growth rate of 0.082 nm/cycle. Layer uniformity is approximately within ±1% of the mean value. MOS capacitors have been fabricated by evaporating aluminium electrodes. CV analysis has been used to determine the bulk and interface properties of the HfO2, and their dependence on pre-clean schedule, deposition conditions and post-deposition annealing. The dielectric constant of the HfO2 is typically 18. On silicon, best results are obtained when the HfO2 is deposited on a chemically oxidised hydrophilic surface. On germanium, best results are obtained when the substrate is nitrided before HfO2 deposition, using an in-situ nitrogen plasma treatment.

The piezoresistance effect is defined as change in resistance due to applied stress. Silicon has a relatively large piezoresistance effect which has been known since 1954. A four point bending setup is proposed and designed to analyze the piezoresistance effect in p-type silicon. This setup is used to apply uniform and uniaxial stress along the crystal direction. The main aim of this work is to investigate the piezoresistive characteristic of p-type resistors as a function of doping concentrations using COMSOL Multiphysics. Simulation results are compared with experimental data.