Germanium (Ge) photodiodes were fabricated with the new RMG crucible materials that were established in this study. Results show that Ge large square patterns with size of 208 µm x 208 µm were unable to be achieved if ion implantation process was used in formation of photodiode. Delamination can be observed on all test samples during polycrystalline silicon (poly-Si) deposition at 620 oC. This result was in contrast to a previous intrinsic Ge test structure, where good formation of squares with size similar to that 208 µm x 208 µm had been successfully attained even with high annealing temperature above 938 oC. This indicates that doping through ion implantation has affected Ge film and caused delamination even at low temperature. However, good formations of Ge stripes were attained along with the ion implantation process in fabricating the photodiode. Results show that the sheet resistance of Ge stripe has significantly decreased compared to previous Ge resistors. The better resistance is due to the thicker (500 nm) Ge layer. In the case of Ge stripes with a p-i-n junction, only small fraction of test samples have shown a diode characteristic but with high leakage current. Results of I-V measurement show that a large fraction of test samples produced resistor characteristics. The high leakage current is believed due to the fact that the Ge films formed at this stage were polycrystalline in structure. Thus the grain size of Ge stripe has affected the performance. Slight changes on the I-V characteristic of single Ge can be observed when samples were tested under illumination. Therefore, it has potential to be used for future development of energy conversion device.

This paper presents the electrical characterisation of germanium stripe resistors produced by Physical Vapour Deposition using a Rapid Melt Growth process with either single or multiple micro-crucible materials. Electrical measurement of single germanium stripe resistors were obtained using a Greek cross test structure whereas four-terminal aluminium rail test structures were used for germanium stripe arrays. The electrical characterisation was conducted under dark conditions. Results showed only a slight reduction in germanium sheet resistance compared to that of as-deposited material even after a high temperature (980 °C) crystal growth process. It is believed that the measurements were compromised by contact and leakage current issues. As a result, the electrical characteristics of crystallised germanium could not be investigated properly and the relationship to Raman measurement was not established.

Post-exfoliation thermal annealing in air and ultrasonic treatments were carried out on mechanically exfoliated MoS2 flakes on oxidized silicon substrates. Ultra-sonication of MoS2 flakes on SiO2 without prior annealing results in almost complete removal of flakes, indicating weak interface bonding. The interface adhesion between MoS2 flakes and the substrate is significantly improved when the samples are annealed at 270 °C as the flakes remain strongly adhered to the substrate during subsequent ultrasonic treatment. We consider that improved adhesion is due to greater contact area between the flakes and the substrate due to effusion of trapped impurities during annealing. Annealing between 75 °C and 175 °C followed by ultrasonic treatment results in small MoS2 fragments on the samples due to breakage and/or partial removal of top layers. It also results in exposing residual adhesive traces on the sample which are caught between the flake and the substrate during repetitive folding of the Scotch® tape during the initial exfoliation. An annealing temperature of 460 °C results in decomposition of MoS2 and formation of MoO3. Optical microscopy, non-contact-mode atomic force microscopy (AFM) and Raman spectroscopy were used for identification of MoS2 fragments and residual traces left on the samples after the post-exfoliation treatments.

This paper presented an evaluation of hafnium dioxide (HfO2) used as insulator and micro-crucible in the modification of rapid melt growth (RMG) structure. A 20 nm HfO2 have been deposited on silicon (Si) and silicon on insulator (SOI) substrates using Atomic Layer Deposition (ALD). Samples encapsulated with HfO2 in the RMG structure shows free from cracks and delamination even heated at higher annealing temperature (1049 oC) that observed by Scanning Electron microscopy (SEM), Transmission Electron Microscopy (TEM) and Focus Ion Beam (FIB). The quality of germanium (Ge) thin-film is characterised using micro-Raman Spectroscopy. Results show that samples with HfO2 microcrucible liner on Si substrate gives the Ge-Ge peak position lies at ~299 cm-1, indicating that the 20 nm HfO2 layer gives slightly tensile strain with a small shift in peak position compared to the bulk reference value of 300.2 cm-1. The Raman peak position for samples on SOI substrate increased approximately 0.3 cm-1 to 299.3 cm-1 indicating lower stress. The Raman peak of this sample had an increased Full width at half maximum (FWHM) of ~3.9 cm-1 which is believed to be mainly due to the presence of HfO2 and scattering of Raman laser.

This paper reports on the enhanced piezoresistive effect in p-type <;110> silicon nanowires, fabricated using a top down approach. The silicon nanowire width is varied from 100 to 500nm with thickness of 200 nm and length of 9μm. It is found that the piezoresistive effect increases when the nanowire width is reduced below 350 nm. Compared with micrometre sized piezoresistors, silicon nanowires have produced up to 50% enhancement. Silicon nanowire with cross-section of (100 × 200 nm) with doping concentration of 3.2 × 10 18 cm -3 has produced a gauge factor of 150. The extracted gauge factors are compared with other silicon nanowire experimental publications. The enhancement in piezoresistive effect by employing non-suspended silicon nanowire is beneficial for new MEMS pressure sensors with medium doping concentrations.

GeON has been investigated as an interfacial layer for high-k gate stacks. Thermally grown GeON layers have been prepared at 550oC and compared with plasma GeON layers prepared at 300oC, The optical band gap of thermally-grown GeON was also determined by spectroscopic ellipsometry to be 4.86 eV. Electrical characterisation of MOS capacitors has yielded interface state densities (Dit) of less than 1012 cm-2eV-1 for all devices using the conductance method.

This paper investigates the characteristics of silicon piezoresistors with various dopin g concentrations and Length/Width dimensions at micro level. The silicon piezoresistors have been produced by conventional fabrication methods. The measurements are conducted on silicon test chips where p-type resistors are fabricated on n type (100) silicon substrates along the <110> direction. A fou r point bending setup has been designed and fabricated for characterizing the piezoresistor sets. The f our point bending setup is used to apply uniform uniaxi al stress along the <110> direction. This experimental result demonstrates a good linear relationship between resistance change and stress applied. The effect of doping concentration on temperature sensitivity is also investigated.

Germanium is an attractive channel material for MOSFETs because of its higher mobility than silicon. In this paper, GeO 2 has been investigated as an interfacial layer for high-k gate stacks. Thermally grown GeO 2 layers have been prepared at 550 °C to minimize GeO volatilization. GeO 2 growth has been performed in both pure O 2 ambient and O 2 diluted with N 2 . GeO 2 thickness has been scaled down to 3.15 nm. MOS capacitors have been fabricated using different GeO 2 thicknesses with a standard high-K dielectric on top. Electrical properties and thermal stability have been tested up to at least 350°C. The k value of GeO 2 was calculated as 4.5. Interface state densities (D it ) of less than 10 12 cm -2 eV 1 have been extracted for all devices using the conductance method.

Germanium is one of the most promising materials for high performance infra-red photovoltaic devices. High quality single-crystal germanium on insulator structures can be produced by a Rapid Melt Growth process. Experiments show that thin-film germanium deposited by physical vapor deposition provides better quality in comparison with chemical vapor deposition. The longitudinal optical Ge-Ge peak in Raman spectrum is shifted from the expected 300.2 cm-1 position due to tensile stress resulting from the thermal expansion differences of the materials. The importance of silicon in the rapid melt process is confirmed by the fact that germanium films on sapphire substrates yielded polycrystalline structure. Films produced at high temperature (980 oC) show full width at half maximum values of 3.3 cm-1 indicating good crystalline quality, comparable to bulk germanium (3.2 cm-1). Thus demonstrating the potential to produce low cost high quality germanium films.

The results on structural damage in germanium wafers caused by hydrogen and helium implants of typical doses used in Smart Cut™ Technology (1–6 × 1016 atoms/cm2) are investigated using Raman mapping and spreading resistance profiling techniques. Raman line‐mapping measurements were performed up to the depth of ~400 nm into a Ge substrate (well beyond the limit of visible light penetration depth) using a bevelling technique. From analysis of the Ge–Ge Raman peak it was found that implantation of H and He introduced a different type of stress, tensile and compressive, respectively and significant structural damage with maximum at the projected range. The obtained data shows that hydrogen incorporation in Ge can act as an acceptor. This is undesirable when the hydrogen ion‐cut technology is applied to high resistivity Ge. The crystalline structure after implantation is completely recovered when annealed at 600 °C for both types of implants. Spreading resistance profiling results reveal that 4−8x1015 acceptors/cm3 remain after 600 °C, and these are thought to be because of vacancy related defect clusters. Copyright © 2011 John Wiley & Sons, Ltd.

The technology for thin Ge layer transfer by hydrogen ion-cut process is characterised in this work. Experiments were carried out to determine suitable hydrogen ion implantation doses in germanium for the low temperature ion cut process by examining the formation of blisters on implanted samples. Raman and Spreading Resistance Profiling (SRP) have been used to analyse defects in germanium caused by hydrogen implants. Bevelling has been used to facilitate probing beyond the laser penetration depth. Results of Raman mapping along the projection area reveal that after post implant annealing at 400 °C, some crystal damage remains, while at 600 °C, the crystal damage has been repaired. SRP shows that some amount of hydrogen acceptor states (~1Î1016 acceptors/cm2) remain after 600 °C. These are thought to be vacancy-related point defect clusters.

This paper reviews the development of germanium technology for applications in high performance CMOS ICs, rf and MMICs. The paper covers the development of MOSFET technology with respect to source/drain doping and gate dielectrics. Germanium has higher junction leakage currents than silicon on account of its lower energy bandgap. It is a scarce material, expensive and the wafer size is limited. To minimize these disadvantages germanium will be employed as a thin layer on an insulator substrate. Various methods of producing germanium-on-insulator (GeOI) substrates are outlined. These include the Smart-cut process, the condensation process starting with SOI wafers and the epitaxial growth of germanium on lattice matched crystalline oxides grown on silicon substrates. Partial GeOI layer techniques reviewed are dislocation necking of solid phase epitaxial layers grown in narrow high aspect ratio trenches and liquid phase epitaxy from rapid melt germanium confined in micro-crucibles. The fabrication of germanium on dielectric substrates such as quartz, sapphire and alumina are also discussed.

An atmospheric plasma activation system has been employed to study its application on low temperature wafer bonding. High bond strength (> 2000 mJ/m2) is achieved by oxygen plasma activation on hydrophilic Si-Si and Si-SiO2 bonding at low temperature annealing. This technique has been proved to cause physical damage to thin SiO2 layers (< 0.5 µm) creating a high density of pin holes resulting in leaky oxides. When high resistivity substrates are employed the pin holes is reduced by nearly a factor of 7. A germanium disc bonded to plasma treated thin oxide on silicon was electrically connected to the substrate. The atmospheric plasma technique is currently best suited for silicon-silicon bonding, standard SOI, MMIC and MEMS technology.

An atmospheric plasma activation system has been employed to study its application on low temperature wafer bonding. Oxygen activation on PECVD oxide for bonding of temperature sensitive materials shows no pin hole when activating oxide with thickness more than 0.25 microns. Activation on thermal oxide by helium plasma also shows a pin hole free oxide. Bond strength approximately 1000 mJ/m2 is achieved after 250 degree celcius post-bond anneal which is about twice the bond strength of non-activated samples. Multiple UV components from the helium plasma were detected by spectograph. These UV spectra might have contributed to the bond strength enhancement in Si-SiO2 bonding.

Germanium (Ge) has been bonded to fine grain alumina (Al2O3) by means of a polished polycrystalline silicon interface layer. After room temperature bonding and subsequent bond strength annealing at 150 oC for 24 hrs, the germanium layer was ground and polished to 100µm. Low temperature Tungsten (W) gate circular geometry devices, W/L = 9, fabricated on this layer exhibited effective mobility values of 150 cm2/Vs. This is much lower than results obtained on equivalent devices on bulk Ge. Improvement in the germanium polish process resulted in transistors with an effective mobility of 415 cm2/Vs, comparable to that of the bulk Ge devices. Low temperature measurement, down to temperatures of 173 K, showed an improvement in device performance resulting in both an increase in effective mobility to 591 cm2/Vs and a decrease in sub threshold slope from 180 mV/dec to 60 mV/dec indicating a reduction in leakage current.

Tungsten gate germanium MOS transistors have been manufactured on bulk germanium platforms. Hole mobility in the range 450 cm2/Vs has been achieved on bulk germanium, but mobility is reduced during the densification of thinner dielectrics at 600C. This may be due to the formation of volatile GeO at the interface during densification. Low temperature measurements of the thinner dielectric device indicate that lattice scattering is dominant at room temperature for the device where the densification was omitted and the excellent subthreshold slopes at low temperatures also indicate devices of good quality.

Al2O3 and HfO2 films were deposited on germanium substrates by atomic layer deposition (ALD) and analyzed by MOS capacitor electrical characterization. In-situ plasma nitridation performed prior to ALD was found to improve the stability of the interface. For Al2O3/GeON/Ge capacitors, a 450°C anneal in nitrogen ambient reduced hysteresis and oxide fixed charge to 90 mV and 1012 cm-2 respectively, with low leakage current density. On the contrary, degradation was observed for un-nitrided Al2O3/Ge capacitors after 300 and 400°C post-metal anneals. HfO2/GeON/Ge capacitors benefitted from a 400°C densification anneal but exhibited degradation after post-metal anneals at temperatures greater than 300°C. This degradation is attributed to the influence of Al electrodes on the HfO2 gate stack. HfO2 is considered to be a suitable material for the gate stack and Al2O3 for the buried dielectric in a GeOI structure.

Hydrogen implantation of germanium is a promising technique for layer transfer. However, both the implantation process, and subsequent heat treatment can create defects in the transferred layer, which detrimentally effect the performance of devices fabricated on these transferred layers. In this study, implanted Germanium wafers were given various anneals and analysed optically and by spreading resistance, to gain insight on the nature of such defects. GeOI layers were produced by thermal splitting of implanted germanium wafers bonded to sapphire handle substrates.

This paper examines the DC power requirements of PIN diodes which, with suitable applied DC bias, have the potential to reflect or to permit transmission of millimetre wave energy through them by the process of inducing a semiconductor plasma layer in the I region. The study is conducted using device level simulation of Sol and bulk PIN diodes and reflection modeling based on the Drude conduction model. We examined five diode lengths (60-140 mu m) and seven diode thicknesses (4-100 mu m) Simulation output for the diodes of varying thicknesses was subsequently used in reflection modelling to assess their performance for 100 GHz operation.It is shown that substantially high DC input power is required in order to induce near total reflection in SOI PIN diodes at 100 GHz. Thinner devices consume less DC power. but reflect less incident radiation for given input power. SOI diodes are shown to have improved carrier confinement compared with bulk diodes (C) 2009 Elsevier Ltd All rights reserved

A low temperature process has been established for the manufacture of self-aligned W gate germanium MOS transistors. Hole carrier mobility in the range 500 - 650 cm(2)V(-1)s(-1) has been achieved. Sub threshold slope, threshold voltage and carrier mobility have been characterised as a function of temperature. The technology has been successfully transferred to both Germanium on sapphire and Germanium on alumina substrates providing an ideal platform technology for System on a Chip.