Storage swapping has been a critical technique used to relieve memory pressure and improve user experience. However, it generates lots of data writes in flash storage, deteriorating the lifetime and performance. In this paper, inspired by empirical studies on swap data access characteristics, we propose a novel data invalidation scheme, namely DISS, which includes two methods. First, a cross-layer swap-data invalidation method is proposed to invalidate swapped-in data at a low cost. Second, a swap data separation method is proposed to schedule swap data and file-backed data into different places. Experimental results show that DISS achieves encouraging flash lifetime and performance optimization.

The pseudo-single-level-cell (pSLC) technique is widely adopted in high-density flash-based storage to mitigate the performance and endurance problem of high-density flash memory. Furthermore, prefetching schemes can compensate for performance differences among storage tiers. Existing prefetchers are implemented in the operating system (OS) or storage layers. However, OS layer prefetchers are conservative since it is a challenge to achieve both high accuracy and large coverage simultaneously. Storage layer prefetchers are sub-optimal due to the performance differences between pSLC and DRAM. In this paper, a cross-layer prefetching framework (CPF) is proposed to prefetch data selectively. The basic idea is that high-accuracy data will be prefetched to DRAM and large-coverage data will be prefetched to the pSLC flash in storage. To make it practical, an adaptive regulator is further designed to dynamically adjust the cross-layer prefetching to ensure accuracy and coverage. Evaluations show that CPF can improve read performance and reduce data transfer costs significantly.

Automatic test paper design is critical in education to reduce workloads for educators and facilitate an efficient teaching process. However, current designs fail to satisfy the realistic teaching requirements of educators, including the consideration of both test quality and efficiency. This is the main reason why teachers still manually construct tests in most teaching environments. In this paper, the quality of tests is quantitatively defined while considering multiple objectives, including a flexible coverage of knowledge points, cognitive levels, and question difficulty. Then, a model based on the technique of linear programming is delicately designed to explore the optimal results for this newly defined problem. However, this technique is not efficient enough, which cannot obtain results in polynomial time. With the consideration of both test quality and generation efficiency, this paper proposes a genetic algorithm (GA) based method, named dynamic programming guided genetic algorithm with adaptive selection (DPGA-AS). In this method, a dynamic programming method is proposed in the population initialization part to improve the efficiency of the genetic algorithm. An adaptive selection method for the GA is designed to avoid prematurely falling into the local optimal for better test quality. The question bank used in our experiments is assembled based on college-level calculus questions from well-known textbooks. The experimental results show that the proposed techniques can construct test papers with both high effectiveness and efficiency. The computation time of the test assembly problem is reduced from 3 hours to 2 seconds for a 5000-size question bank as compared to a linear programming model with similar test quality. The test quality of the proposed method is better than the other baselines.

Personalized learning path recommendation is widely studied to address the cognitive overload and learning disorientation problem in e-learning platforms. Yet, how to recommend learning materials for learners so that targeting their learning objectives with the highest efficiency has not been addressed. Driven by this problem, this paper proposes a prototype to generate the most efficient learning strategies in the learning process for reaching learning objectives, it takes the learning ability of learners into consideration, and adaptively generates the optimal strategy in the learning process. A case that knowledge concepts have hierarchical relationships based on difficulty in one knowledge topic is studied, which is named series learning in this paper. Specifically, a learning state transition model is designed for selecting the optimal learning strategies in the learning process with the consideration of the changing learning ability of learners. Based on this model, a dynamically programming (DP) based method and a greedy-based method are designed to generate learning strategies with high efficiency. Experiments are conducted in both simulated and real learning scenarios. Results show that the proposed scheme significantly outperforms the baseline method.

In the existing software development ecosystem, security issues introduced by third-party code cannot be overlooked. Among these security concerns, memory access vulnerabilities stand out prominently, leading to risks such as the theft or tampering of sensitive data. To address this issue, software-based defense mechanisms have been established at the programming language, compiler, and operating system levels. However, as a trade-off, these mechanisms significantly reduce software execution efficiency. Hardware-software co-design approaches have sought to either construct entirely isolated trusted execution environments or attempt to partition security domains within the same address space. While such approaches enhance efficiency compared to pure software methods, they also encounter challenges related to granularity of protection, performance overhead, and portability. In response to these challenges, we present the DASICS (Dynamic in-Address-Space Isolation by Code Segments) secure processor design, which offers dynamic and flexible security protection across multiple privilege levels, addressing data flow protection, control flow protection, and secure system calls. We have implemented hardware FPGA prototypes and software QEMU simulator prototypes based on DASICS, along with necessary modifications to system software for adaptability. We illustrate the protective mechanisms and effectiveness of DASICS with two practical examples and provide potential real-world use cases where DASICS could be applied.

Non-volatile memory (NVM) is expected to be the second tier of memory in two-tier memory systems. However, because of the limited write endurance, it is vital to reduce the number of writes on NVM. Large-scale nested loops are the performance bottleneck in programs since the data cannot be held on the first tier of memory and then causes many write operations on NVM. Loop tiling groups iterations and loop interchange changes the execution order of the loop to improve data locality and thus reduce communication with NVM. However, research that combines loop interchange and loop tiling for minimizing writes on NVM is uncommon. In this paper, we propose a new loop tiling scheme and combine the loop interchange to solve these issues. Specifically, we propose a strategy to generate the legal tile shape, which is a parallelogram, first. Then, we propose an optimal tile size selection technique to minimize the write operations on NVM. In addition, we adopt the loop interchange technique to help loop tiling generate an optimal tile size for multi-dimensional loops. Finally, we schedule the accessing operations and computations in a pipeline fashion to cover the NVM latency. Experiments show that the proposed scheme can reduce the write on NVM efficiently. In addition, for 2-dimensional loops, NVM latency can be completely hidden.

Predicting hard disk failure effectively and efficiently can prevent the high costs of data loss for data storage systems. Disk failure prediction based on machine learning and artificial intelligence has gained notable attention, because of its good capabilities. Improving the accuracy and performance of disk failure prediction, however, is still a challenging problem. When disk failure is about to occur, the time is limited for the prediction process, including building models and predicting. Faster training would promote the efficiency of model updates, and late predictions not only have no value but also waste resources. To improve both the prediction quality and modeling timeliness, a two-layer classification-based feature selection scheme is proposed in this paper. An attribute filter calculating the importance of attributes was designed, to remove attributes insensitive to failure identification, where importance is gained based on the idea of classification tree models. Furthermore, by determining the correlation between features based on the correlation coefficient, an attribute classification method is proposed. In experiments, the models of machine learning and artificial intelligence were applied, and they included naïve Bayesian, random forest, support vector machine, gradient boosted decision tree, convolutional neural networks, and long short-term memory. The results showed that the proposed technique could improve the prediction accuracy of ML/AI-based hard disk failure prediction models. Specifically, utilizing random forest and long short-term memory with the proposed technique showed the best accuracy. Meanwhile, the proposed scheme could reduce training and prediction latency by 75% and 83%, respectively, in the best case compared with the baseline methods.

In this paper, a novel hybrid scratchpad memory (SPM) with SRAM and racetrack memory (RM) is proposed. The basic idea is to smartly place data on SPM by taking the advantages of these two memories. First, a metric is proposed to represent the access cost of data; Second, a data placement scheme is proposed based on the metric; Finally, to maximize the size of SPM, a scheme is further proposed to minimize the size of SRAM. Experimental results show that the proposed scheme reduces the shift operations of RM by 80.12% and reduces the cost of SPM by 80.72% with only 17.63% SRAM compared with a baseline SPM with pure RM.

Racetrack memory (RTM), which consists of multiple domain block clusters (DBC) and access ports, is a novel non-volatile memory and has potential as scratchpad memory (SPM) in embedded devices due to its high density and low access latency. However, too many shift operations decrease the performance of RTM and cause un-predictable performance. In this paper, we propose three schemes to optimize the performance of RTM from different aspects, including intra-DBC, inter-DBC, and hybrid SPM with SRAM and RTM. Firstly, a balanced group-based data placement method for the data layout inside one DBC is proposed to reduce shifts. Second, a grouping method for the data allocation among DBCs is proposed. It helps with the shift reduction while using fewer DBCs by using one DBC as multiple DBCs. Finally, we use SRAM to further help the cost reduction, and a cost evaluation metric is proposed to assist the shrinking method which determines the data allocation for hybrid SPM with SRAM and RTM. Experiments show that the proposed schemes can significantly improve the performance of pure RTM and hybrid SPM while using fewer DBCs.

With the development of noisy intermediate-scale quantum machines, quantum processors show their supremacy in specific applications. To better understand the quantum behavior and verify larger quantum bit (qubit) algorithms, simulation on classical computers becomes crucial. However, as the simulated number of qubits increases, the full-state simulation suffers exponential memory increment for state vector storing. In order to compress the state vector, some existing works reduce the memory by data encoding compressors. Nevertheless, the memory requirement remains massive. Meanwhile, others utilize compact decision diagrams (DD) to represent the state vector, which only demands linear memory size. However, the existing DD-based simulation algorithm possesses many redundant calculations that require further exploration. Besides, the traditional normalization-based nodes merging method of DD amplifies the side influences of approximate error. Therefore, to tackle the above challenges, in this paper, we first fully explore the redundancies in the recursive-based DD simulation (RecurSim) algorithm. Inspired by the regularities of the quantum circuit model, a scale-based simulation (ScaleSim) algorithm is proposed, which removes plenty of unnecessary computations. Furthermore, to eliminate the influences of approximate error, we propose a new pre-check DD building method, namely PCB, which maintains the accuracy of DD representation and produces more memory saving. Comprehensive experiments show that our method achieves up to 24124.2 × acceleration and 3.2 × 10^7× memory reduction than traditional DD-based methods on quantum algorithms while maintaining the representation accuracy.

Knowledge tracing models based on deep neural networks are currently widely studied to enhance personalized learning. However, to ensure the practical deployment of DNN-based KT models, prediction accuracy, training efficiency, and interpretability should be greatly improved. In this paper, we observe that the prediction accuracy of KT models can be improved by clustering the features of both students and questions. Based on this observation, a distributed KT scheme is proposed: (1) it classifies both students and questions based on clustering technology to reduce the interaction between different feature data to improve the prediction accuracy; (2) models for different classifications are trained in parallel in this distributed deployment architecture to improve the training efficiency; (3) the combination of a students’ knowledge state matrix and an RPa-LLM model is designed to display the knowledge status of students in the learning process, which can be used to build students’ portraits, thus improving the interpretability of the model. Real educational data are collected to conduct experiments. The results show that the proposed scheme improves both prediction accuracy and training efficiency by 4.08% and 67.28%, respectively, compared to the baseline methods. Furthermore, the proposed method maintains the interpretability of KT models, making it suitable for practical deployment.

Nowadays, household NAS service provides consumer device users a convenient way to extend their storage space through WLAN. As the core of NAS service, distributed file system’s objective is to make the whole system provide a good user experience. However, it is normal for consumer devices to work under unstable network conditions, which can significantly degrade the user experience. Moreover, user behavior is getting more complicated, which means traditional mainstream optimization techniques have little effect in this case. To improve user experience, this paper proposes several practical optimization solutions for a lightweight distributed file system. First, a set of client-side cache optimization schemes, including swap-based persistent caching and cross-device cache prefetching with the Markov method, are proposed to reduce remote access latency. Second, a task-aware write-back scheduling scheme is proposed to enhance the cache synchronization efficiency. Finally, a simple protocol based on multiple readers and single writer for multi-device access control is proposed. Experiments on real devices show that the average access latency can be reduced by 29.7% with swap-based client-side persistent caching. Cross-device prefetching reduces around 33% access latency in the best case. Average cache synchronization latency is reduced by 13.7% and the worst synchronization latency is reduced by 63.7% with write-back scheduling. Multi-device access protocol induced negligible overhead but works effectively on controlling concurrent accesses.

Currently, most of the Flash-based storage systems reduce the performance gap between the main memory and storage by data prefetching. However, conventional prefetching techniques perform well on hard disk drives but have limited effectiveness and efficiency on Flash. It is because the complicate data access patterns in modern systems have not been well considered. In this paper, we propose SFP, a smart file-aware prefetching scheme for Flash-based storage systems. SFP demonstrates that prefetching accuracy and efficiency can be improved comprehensively in a file-aware approach. Furthermore, three schemes are proposed: file access pattern learning, dynamic window-based file prefetching, and learning model size optimization. Experiments on the real server show that SFP reduces the access latency by up to 40% compared with the state-of-the-art with low memory and computation cost.