This article presents a 300-GHz-band amplifier-last outphasing phased-array transmitter with path mismatch calibration in a 65-nm CMOS technology. Calibration is essential for mitigating impairments in outphasing systems used for wideband communication. The transmitter integrates two independent sub-THz LO generation chains to calibrate the phase mismatch between two paths and configure the phase delay between different phased-array elements. An integrated RF outphasing amplifier calibrates the amplitude mismatch and improves the transmitter's effective isotropic radiated power (EIRP). After calibration, the transmitter exhibits a 3.3-dB improvement in error vector magnitude and supports 16QAM modulation at 52Gb/s over a distance of 9cm. It achieves a peak EIRP of 8.9dBm at 246GHz, with a minimum EIRP of 5.0dBm across the frequency range from 237 to 250GHz. An 8x1 phased-array transmitter is implemented, demonstrating a main lobe scanning range of +/- 12 degrees in the $E$ -plane.

This paper presents a 300-GHz-band 2D $4 \times 4$ bi-directional phased-array transceiver with on-chip half-wavelength-spaced array and ultra-low power consumption in 65-nm CMOS. Each element comprises a phased shifter, doubler, injection-locked tripler, sub-harmonic mixer, and on-chip dipole antenna, occupying a compact core area of 0.30 mm2. The power consumption of each element is 26 mW. The $4 \times 4$ phased-array features pitches of 0.49 - and 0.50 -wavelength in the E - and H planes, respectively, with measured main-beam scanning angles of $\pm 32^{\circ}$. The single chip achieves a peak EIRP of −17.1 dBm at 256 GHz.

This article describes a 300-GHz-band four-element amplifier-last phased-array transmitter (TX) that has been implemented in a 65-nm CMOS technology. Each chip integrates four TX elements with a power amplifier (PA)-last architecture. The proposed wideband PA employs an optimized transistor layout to reduce parasitic parameters, enhancing the transistor-gain corner frequency from 250 to 300 GHz for an 8 mu m x60 nm device. A dual-peak G(max)-core topology is adopted to achieve wideband inter-stage conjugate impedance matching. Operating from 237 to 267 GHz, the PA provides over 20 dB of gain while eliminating the need for power combining, thereby improving both TX output power and area efficiency. The TX also integrates an on-chip Vivaldi antenna with a measured realized gain of 5.0 +/- 1.0 dBi across 220-280 GHz after proton irradiation. The four-element phased-array TX achieves a maximum data rate of 60 Gb/s using 16 quadrature modulation (QAM) over 6 cm and 56 Gb/s using quadrature phase shift keying (QPSK) over 20 cm, with a peak effective isotropic radiated power of 16.2 dBm at 245 GHz. A 2-D 4 x 4 beam pattern was measured using a stacked printed circuit board (PCB) configuration, demonstrating scanning coverages of +/- 24 degrees in the E-plane and +/- 28 degrees in the H-plane.

This work presents a D-band high-power-density four-element phased-array transceiver for 6G user equipment (UE). Conventional designs require large multi-stage LO generation circuits for D-band up/down conversion, making it difficult to achieve compact size and low-power consumption. To address this, we propose an integrated LO chain using an injection-locked tripling phase shifter (ILTPS), which enables both frequency tripling and phase shifting within a single circuit without multi-stage amplifiers. The ILTPS achieves an area of 0.088 mm(2) and a power consumption of 15 mW. In addition, to realize high power density, the transceiver integrates a bi-active sub-harmonic mixer (BA-SHM) and a D-band PA/LNA with PA-sharing TDD switching. An eight-element antenna-in-package (AiP) module using two transceiver ICs operates in the 142-164-GHz frequency range, achieving an EIRP of 25.7 dBm and a maximum data rate of 56 Gbps. The power consumption per element is 150 mW in TX mode and 93 mW in RX mode with 1 V VDD. The active area of this transceiver is 8.5 mm(2), and it is implemented using a 65 nm CMOS process.

This paper introduces a testbed for joint radar-communication (JRC) utilizing frequency-division multiplexing (FDM) in the D-band (116–170 GHz). It employs a wideband 65 nm CMOS transceiver, originally designed for high-throughput communications. Utilizing external frequency-modulated continuous-wave (FMCW) chirps, it achieves a range resolution of 13.6 mm and sub-millimeter accuracy in radar-only mode. In simultaneous JRC operation, it sustains a 24 mm range resolution while supporting data rates up to 20 Gb/s using 16-QAM and 32-QAM modulation schemes. A single-transmitter, single-receiver (1T1R) configuration is used to demonstrate radar and communication coexistence within a shared spectrum, whereas an extended single-transmitter, two-receiver (1T2R) setup validates the simultaneous demodulation of both direct and reflected links, demonstrating multi-user capabilities. Doppler measurements are used to verify low-speed velocity sensing via segmented acquisition, illustrating how factors such as distance, radar cross section (RCS), and beam alignment together impact signal-to-noise ratio (SNR), radar visibility, and the quality of the communication link. This system-level validation marks the first experimental proof of a communication-focused architecture in the D-band, establishing the feasibility of scaling existing CMOS hardware for future integrated system-on-chip (SoC) solutions capable of simultaneous high-speed communication and fine-resolution sensing.

This paper introduces a testbed for joint radar-communication (JRC) utilizing frequency-division multiplexing (FDM) in the D-band (116-170 GHz). It employs a wideband 65 nm CMOS transceiver, originally designed for high-throughput communications. Utilizing external frequency-modulated continuous-wave (FMCW) chirps, it achieves a range resolution of 13.6 mm and sub-millimeter accuracy in radar-only mode. In simultaneous JRC operation, it sustains a 24 mm range resolution while supporting data rates up to 20 Gb/s using 16-QAM and 32-QAM modulation schemes. A single-transmitter, single-receiver (1T1R) configuration is used to demonstrate radar and communication coexistence within a shared spectrum, whereas an extended single-transmitter, two-receiver (1T2R) setup validates the simultaneous demodulation of both direct and reflected links, demonstrating multi-user capabilities. Doppler measurements are used to verify low-speed velocity sensing via segmented acquisition, illustrating how factors such as distance, radar cross section (RCS), and beam alignment together impact signal-to-noise ratio (SNR), radar visibility, and the quality of the communication link. This system-level validation marks the first experimental proof of a communication-focused architecture in the D-band, establishing the feasibility of scaling existing CMOS hardware for future integrated system-on-chip (SoC) solutions capable of simultaneous high-speed communication and fine-resolution sensing.

This paper proposes a high-power-density 150 GHz phased-array transceiver designed for 6G user equipment (UE) modules, utilizing $65-\text{nm}$ CMOS technology. An 8 -element AiP module using two transceiver ICs operates in the 142-164 GHz frequency range, achieving an EIRP of 26 dBm and a maximum data rate of 56 Gbps. The power consumption per element is 150 mW in TX mode and 93 mW in RX mode.

This paper presents a 300 GHz-band amplifier-last outphasing transmitter with path mismatch calibration in 65nm CMOS. The transmitter integrates two independent sub-THz LO generation chains to calibrate the mismatch between two paths in the outphasing topology. After the calibration, the proposed transmitter achieves a minimum EIRP of 5.0dBm over a frequency range from 237GHz to 250GHz, with a maximum of 8.9dBm EIRP at 246GHz. It supports a data rate of 52Gb/s in 16QAM, with a communication distance of 9cm.

This work presents a D-band (110-170 GHz) CMOS transceiver (TRX) chipset that covers a 56-GHz (114-170 GHz) signal-chain bandwidth. Both the transmitter (TX) and the receiver (RX) operate as heterodyne architectures with external intermediate frequency (IF) and local oscillator (LO) signals. An eight-way low-Q power-combined power amplifier (PA), a two-way low-Q power-combined low-noise amplifier (LNA), wideband-impedance-transformation passive mixers, common-source-based cascaded distributed amplifiers (DAs), and a low-loss wideband chip-to-waveguide printed circuit board (PCB) transition are proposed with improved bandwidth and linearity to support high-order wideband quadrature amplitude modulation (QAM) signals. The TRX chipset was fabricated using a 65-nm CMOS process. The TX achieves a 13-dBm saturated output power at 130 GHz with 1150-mW dc power. The RX achieves a 12-dB noise figure (NF) with 550-mW dc power. The proposed TRX chipset achieves a data rate of 200 Gb/s by 32QAM in the single-input-single-output (SISO) over-the-air (OTA) measurement at 0.32 m. A data rate of 150 Gb/s by 16QAM is realized with 43-dBi antennas at 15 m. Additionally, a 640-Gb/s 4 x 4 OTA line-of-sight multiinput multioutput (LOS-MIMO) is demonstrated at 0.52 m.

This work presents a D-band bi-directional CMOS double-balanced mixer (DBM) supporting data rates over 160 Gb/s with a 58-GHz RF bandwidth (112-170 GHz). The mixer employs four identical NMOS passive switches (12 mu m/60 nm) in a DBM topology, providing the isolation between RF, LO, and IF ports. Both IF and RF are bidirectional, enabling up conversion and down conversion. The proposed mixer is fabricated in a 65-nm CMOS process with an integrated LO-driver amplifier. LO amplifier has a 9.5-dB simulated gain and an 8-dBm saturated output power. The total area, including RF and DC pads is 0.7749 mm2. The measurement result shows a -12.5-dB conversion gain in both directions with differential signals and a 3-dB extra loss in a single-ended configuration. OP1dB is -13.5 dBm for up conversion and -5.5 dBm for down conversion. In modulated signal measurements, the mixer handles a 40-GHz bandwidth OFDM 16-QAM signal centered at 135 GHz, demonstrating a 160-Gb/s data rate in both up conversion and down conversion.

A D-band (114--170GHz) CMOS transceiver (TRX) chipset covering a 56GHz signal-chain bandwidth with a 640-Gb/s data rate is proposed in this work. The design includes an 8-way low-Q power-combined power amplifier (PA), a 2-way low-Q power-combined low noise amplifier (LNA), wideband-impedance-transformation mixers, and common-source-based cascaded distributed amplifiers (DA) to improve bandwidth and linearity. The proposed TRX chipset achieves a 200Gb/s SISO data rate and a 640Gb/s MIMO data rate.

A D-band wideband passive single-ended upconversion mixer with controlled LO feedthrough in 65-nm CMOS process is presented in this letter. The LO feedthrough was controlled by the varactor and the neutralizing transmission line between the LO and RF ports of the mixer. In measurement, the proposed passive single-ended mixer had a conversion gain of -13.0 +/- 1.5 dB with an ultrawide 3-dB bandwidth from 110 to 160 GHz. The LO feedthrough suppression was from -38.9 to -24.4 dB at 135 GHz by changing the varactor bias. The measured OP1dB was -12.5 dBm at center frequency. The chip occupies 0.35 mm(2), including pads.

This paper presents a sub-THz (88-136GHz) full-duplex phased-array transceiver integrating an RF self-interference canceller with differential-feeding full-duplex antennas. The LO phase generation chain controls differential transmitter outputs for the phased-array operation. In the over-the-air measurement, the proposed full-duplex transceiver achieves 6Gb/s in 8PSK and 4Gb/s in 16QAM. The self-interference suppression is improved by 20dB when the self-interference canceller is turned on. The transceiver also achieves a 112Gb/s data rate by wideband amplifiers and the neutralized mixer.

Because the vast majority of the frequencies are unallocated and atmospheric absorption is low above 250GHz, 300GHz-band transceivers are appealing for the sixth-generation (6G) wireless communication technologies to support over 100Gb/s data rate. The main challenge of the 300GHz-band transmitter (TX) is achieving a large equivalent isotropic radiated power (EIRP) to compensate for the high free-space loss. One solution is to adopt a two-dimensional (2D) phased-array to boost the antenna gain and enable beam steering, which is much more practical than a high-gain antenna or lens. Another way is increasing the output power of each TX element. There are compound semiconductor processes with transistors exhibiting high unity-power-gain frequency (f max ) that can easily achieve this target; however, they tend to be incompatible with digital circuits and are expensive, which make them less practical. CMOS processes enable RF front-end circuits to integrate with baseband circuits at a much lower cost, but their low f max degrades power-amplifier (PA) performance. To address the f max limitation of CMOS, Fig. 24.3.1 shows some recent 300GHz-band TX architectures. The multiplier-last architecture can generate high TX output power, however, the constellation maps of higher-order modulation schemes are degraded and thus fail to support higher data rates [1]. To satisfy its mixer linearity requirement, the square mixer-last architecture needs to operate at power back-off (PBO), and it consumes a lot of area due to power-combining [2]. The sub-harmonic mixer-last architecture suffers from low output power and needs PBO in the TX [3]. While the outphasing topology can operate at around output power at 1dB compression point (OP 1dB ), the generation of the outphasing angles is problematic in digital baseband because their operation mechanism is intrinsically nonlinear [4]. Because of the absence of an RF PA, all the above works suffer from small EIRP, low power-added efficiency, and large chip area.

As the CMOS transceiver reaches the sub-millimeter wave operating frequency, its circuit area cannot keep up with the shrinkage of the 0.5λ0 × 0.5λ0 area limit for the typical 2-dimensional (2D) tile-based phased array topology. This article proposes an end-fire on-chip Vivaldi antenna on a standard 65-nm CMOS process for the 300 GHz band operation. The Vivaldi architecture was chosen for its broadband and end-fire radiation characteristics. End-fire antenna is required for slat array topology, which enables 2D array implementation for transceivers with circuit area above 0.5λ0 × 0.5λ0. The antenna length was shortened to maximize beamwidth and reduce area. Additionally, comb-shaped slots were added to suppress side lobes and back radiation caused by the short length. To prevent higher mode surface waves from distorting the antenna radiation pattern and reducing efficiency, the substrate was thinned to 50 m. A dual-layer proton irradiation process increases the substrate resistivity to 1 kΩ-cm, allowing high-efficiency on-chip antenna implementation on low-cost CMOS processes. The manufactured on-chip Vivaldi antenna has an area of 0.45λ0 × 0.45λ0, with measurement results showing 6 dBi gain with 1 dB flatness from 220 GHz to 320 GHz (37% bandwidth) and 76° E-plane beamwidth at 270 GHz with 87% efficiency. A 1 × 4 slat array implementation using the proposed on-chip Vivaldi antenna has been demonstrated, with measurement results showing a 56° beam steering range across the E-plane.

This work presents the development of a dual-layer proton irradiation profile to decrease the fluence required to create a thermally stable localized high-resistivity silicon (HR-Si) substrate for on-chip passive component enhancement and to create a guard band to suppress noise coupling. Additional irradiation was done on the Si-SiO2 interface to prevent conductive layer formation and reduce the main irradiation's fluence requirement. The thermally stable dual-layer profile was optimized experimentally by applying several interface and main irradiation fluence combinations to the on-chip inductor and comparing the quality factor before and after annealing. The optimum total fluence found for the dual-layer profile was 4 x 10(14) cm(-2) with a measured mask-edge margin distance of 22 mu m, corresponding to 60 % fluence reduction and 56 % margin reduction compared to conventional proton irradiation with 10(15)-cm(-2) fluence. Adding a 20-mu m-thick guard band formed by dual-layer proton irradiation between two circuits introduced 5 -dB noise coupling suppression at 1 GHz, with a further 2.5 -dB increase every time the thickness was doubled.

The escalating demand for enhanced wireless communication performance has spurred significant interest in sub-THz frequency bands, notably the J-band (220-325GHz). This band stands out due to an established IEEE standard (802.15.3d), which supports channel widths of up to 69GHz. However, designing amplifiers for such high frequencies requires innovative approaches, such as adopting mixer-last or mixer-first topologies, where the IF amplifiers provide the necessary amplification. Additionally, achieving satisfactory power levels involves the integration of phased-array structures, underscoring the importance of area minimization [1], [2]. This paper delves into the methodologies associated with device de-embedding and modeling. It further details the design of a bi-directional IF amplifier, realized in a 65nm CMOS process with a core area of 1.45x0.3mm2. The amplifier’s measured performance achieves a 14dB gain across a 25GHz bandwidth (35-60GHz) in both transmission directions, an 8.4dB noise figure (NF) for the LNA, and a 7dBm OIP3 for the PA. It also supports 125Gb/s communication employing 32QAM modulation, which significantly advances sub-THz wireless communication.

This paper presents total ionizing dose effect on a Ka-band CMOS beam forming IC for spaceborne deployable membrane phased-array antenna and the deployable phased-array antenna configuration is introduced. Unlike the general aerospace ICs, the BFIC can’t be protected by a metal shield because of the deployability and phased-array configuration. Because of this BFICs could receive a dose of more than 1 Mrad. Furthermore, this paper explains the configuration of the prototype phased-array transceiver and BFIC. The BFIC was designed using a 65 nm CMOS process. The phase shifter in the BFIC uses a radiation tolerant configuration. The BFIC was irradiated up to 10 Mrad, and the radiation tolerance of the BFIC was evaluated from the changes in output power, power consumption, P1dB, S-parameters, and phase. In the irradiation of this BFIC up to 10 Mrad, the change in gain was 0.86 dB and the maximum change in phase was 2.5 degrees. Compared to conventional beamforming ICs, the change of the gain and phase is suppressed to 34 % and 42 %, respectively, even at 10 times higher total dose amount. It was found that the radiation tolerance of this BFIC has been greatly improved. This showed that these BFICs can work normally at radiation doses up to 10 Mrad.

Lightweight and deployable phased arrays are important in Small-Satellite (Small-Sat) constellation systems to reduce price and increase link distance. This article proposes a Ka-band deployable active phased-array TX on a 4-layer liquid crystal polymer (LCP) board for a lightweight and high stowage rate solution to break through the trade-off between high antenna aperture size and small form factor in phased arrays. This article describes detailed designs of the phased array and its building blocks with the proposed 4-layer LCP substrate structure. Assembled with the beamformer ICs (BFIC), a Ka-band $8 \times 4$ -element deployable active phased-array TX on the 4-layer LCP substrate is fabricated. The proposed deployable phased-array TX can steer the beam from −50° to 50°. The phased-array TX can drive 32-APSK DVB-S2 signal with a −28.7 dB EVM as well, revealing that the deployable phased-array TX performs with high phased-array performance. Furthermore, the TX achieved the lightest and thinnest phased array with 0.96 kg/m2 areal mass and 0.9 mm thickness. This groundbreaking research sets the stage for the realization of affordable and user-centric satellite communication (SATCOM) in low-earth orbit (LEO).

A $Ka$ -band 64-element deployable active phased-array transmitter (TX) on a hetero segment liquid crystal polymer (LCP) substrate for small satellites is proposed. The proposed phased-array TX achieved a large array size implementation and a small form factor with integrated six-layer and two-layer LCP substrates. Antenna and transmission line designs considering hetero layer structure are presented in detail. Achieving 46.7 dBm electronically isotropically radiated power (EIRP), the proposed phased-array TX can support 256-APSK DVB-S2X. As a result, the proposed deployable active phased-array TX successfully realizes low-launch cost with a 9.65 g lightweight and large antenna aperture size with superior EVM performance.