In this paper, the dependence of MOSFET performance on the channel stress is characterized in depth. The tensile and compressive stresses are applied to CMOSFET using a nitride film which is used for the contact etch stop layer (CESL). Drain current of NMOS and PMOS is increased by inducing tensile and compressive stress, respectively, due to the increased mobility as well known. In case of NMOS with tensile stress, both decrease of the back scattering ratio () and increase of the thermal injection velocity () contribute the increase of mobility. It is also shown that the decrease of the is due to the decrease of the mean free path (). On the other hand, the mobility improvement of PMOS with compressive stress is analyzed to be only due to the so increased because the back scattering ratio is increased by the compressive stress. Therefore it was confirmed that the device performance has a strong dependency on the channel back scattering of the inversion layer and thermal injection velocity at the source side and NMOS and PMOS have different dependency on them.

This paper shows that dc device performance and reliability characteristics of CMOSFETs do not have the same dependence on the film stress of contact etch stopping layers (CESLs) in strained silicon technology. Two kinds of CESLs, namely, plasma-enhanced chemical vapor deposition (PE-CVD) SiN and low-pressure CVD SiON, with tensile and compressive stresses, respectively, were used to induce channel stress. To further analyze the effects of stress, the film stress of PE-CVD SiN was intentionally split into compressive stress and tensile stress. It is shown that the initial Dit of NMOS with a tensile stress film is less than that with a compressive stress, whereas in the case of PMOS, compressive stress demonstrated less Dit than the tensile-stress film. However, device degradation by hot and cold carriers is heightened more by tensile stress than by compressive stress for both NMOS and PMOS. Therefore, the compressive stress is desirable to improve hot-carrier immunity in NMOSFETs, whereas the tensile stress is necessary to improve the dc device performance. Hence, the simultaneous consideration of reliability characteristics and dc device performance is highly necessary in the stress engineering of nanoscale CMOSFETs.

In this paper, we investigated the device performance and negative bias temperature instability (NBTI) degradation for thermally nitrided oxide (TNO) and plasma nitrided oxide (PNO) in nanoscale p-channel metal oxide semiconductor field effect transistor (PMOSFET). PNOs show the improvement of dielectric performance compared to TNO with no change of the device performance. PNOs also show the improvement of NBTI immunity than TNO at low temperature stress, whereas NBTI immunity of PNO with high N concentration can be worse than TNO at high temperature stress. Recovery effect of NBTI degradation of PNO is lower than that of TNO and it is increased as the N concentration is increased in PNO because the dissociated Si dangling bonds and generated positive oxide charges are repassivated and neutralized, respectively. Moreover, complete recovery of ΔVth is dominated by neutralization of positive oxide charges. Therefore, N contents at polycrystalline Si/SiO2 interface as well as N contents at Si/SiO2 interface can affect significantly on NBTI degradation and recovery effect.

In this paper, the reliability (NBTI degradation: ${\Delta}V_{th}$) and device characteristic of nano-scale PMOSFET with plasma nitrided oxide (PNO) is characterized in depth by comparing those with thermally nitrided oxide (TNO). PNO case shows the reduction of gate leakage current and interface state density compared to TNO with no change of the $I_{D.sat}\;vs.\;I_{OFF}$ characteristics. Gate oxide capacitance (Cox) of PNO is larger than TNO and it increases as the N concentration increases in PNO. PNO also shows the improvement of NBTI characteristics because the nitrogen peak layer is located near the $Poly/SiO_2$ interface. However, if the nitrogen concentration in PNO oxide increases, threshold voltage degradation $({\Delta}V_{th})$ becomes more degraded by NBT stress due to the enhanced generation of the fixed oxide charges.

In this paper, novel Ni Germanosilicide technology using the 1%-nitrogen doped Ni and pure Ni stack structure has been proposed for nano-scale CMOS technology. The Ni Germanosilicide is formed on the Si0.8Ge0.2 layer which is known as an optimal composition for strained silicon application. Proposed structure showed much better thermal stability than pure Ni case. Silicide characteristics such as the sheet resistance, the interface uniformity of silicide/SiGe, surface roughness, and depth profile of the Ni, Si, and Ge showed little degradation even with the high temperature post-silicidation annealing at 600 for 30 min. Therefore, the proposed method is highly promising for nano-scale CMOS technology.

Oxide in Nano Scale PMOSFET’s In-Shik Han, Hee-Hwan Ji, Tae-Gyu Goo, Ook-Sang You, Won-Ho Choi, Min-Ki Na, Ga-Won Lee, Yong-Goo Kim, Sung-Hyung Park, Heui-Seung Lee, Young-Seok Kang, Dae-Byung Kim and Hi-Deok Lee Dept. of Electronics Engineering, Chungnam National University, Yusong-gu, Daejeon 305-764, Korea Phone: +82-42-821-6868, Fax: +82-42-823-9544, *E-mail: hdlee@cnu.ac.kr Magnachip Semiconductor Inc., Hungduk-gu, Cheongju, Choongbuk, 361-725, Korea

In this paper, novel Ni germanosilicide technology using NiPt alloy and Co overlayer has been proposed. Using the Co overlayer after NiPt deposition on Si 1-x Ge x , the formation temperature of low resistive Ni germanosilicide is lowered with high thermal stability. The thermal stability of Ni germanosilicide with different Ge fraction in is also characterized. The sheet resistance degrades as increasing the Ge fraction (x) in Si 1-x Ge x when NiPt/TiN is used. However, using the Co overlayer, the sheet resistance property among Ni germanosilicide formed with different Ge fraction is improved greatly compared with those of NiPt/TiN case (without Co overlayer). Therefore, low-temperature formation of highly thermal robust Ni germanosilicide can be achieved through the NiPt/Co/TiN tri-layer.

In this paper, thermally stable Ni-germanosilicide technology utilizing Ni-Pd alloy and Co/TiN capping layer (Ni-Pd/Co/TiN tri-layer) is proposed for high performance strained-Si CMOS technology. The proposed Ni-germanosilicide technology exhibits low temperature silicidation with a wide temperature window for rapid thermal process (RTP). Moreover, sheet resistance shows stable characteristics in spite of the high temperature postsilicidation annealing up to 700 for 30 min. In addition, the surface of Ni-Pd/Co/TiN structure is much smoother than that of Ni/Co/TiN structure for both before and after the postsilicidation annealing. Therefore, the Ni-germanosilicide using the Ni-Pd/Co/TiN tri-layer is highly promising for future SiGe based nanoscale CMOS technology.

In this paper, the electrical properties of NiSi have been characterized using multi capping layer structure for nano CMOS application. We have investigated the formation and thermal stability of Ni silicide using Ni, Ti and TiN capping layers (Ti/Ni/TiN) as a function of Rapid Thermal Processing (RTP) temperature. It was shown that the NiSi with multi capping layer has lower sheet resistances than that with single capping (TiN) layer. NiSi with multi capping layer also showed much better thermal stability. It was verified that the formation Ni-Ti-Si ternary like layer at the top region of thhe NiSi results in improvement of thermal stability.

In this paper, it is presented that flicker (1/f) noise of ultra thin gate oxide can be improved by initial oxidation and subsequent plasma nitridation(PN). PN which raises Nitrogen peak upward from the Si/Oxide interface to gate polysilicon/Oxide interface is adopted mainly to improve the life time such as Negative-Bias Temperature Instability (NBTI) and hot carrier in Nano CMOS technology. Three different types of initial oxidation prior to plasma nitridation are investigated. One is slow thermally grown oxide(STO) in very small Oxygen ambient, another is rapid thermally grown oxide(RTO) and the other is grown in Nitrous oxygen ambient (NO). Oxide thickness of all splits is about 14.5< Then, it is shown that STO has the lowest drain current noise power (Sid) among the splits. The interface trap densitie (Dit) of each oxide is characterized using charge pumping method. Finally, we reached a conclusion that the 1/f noise can be significantly reduced by initial STO and Plasma Nitridation in Nano CMOS technology.

This paper presents the depth profile of oxide trap density, extracted from the dual gate processed thermally grown oxide in NO ambient and remote plasma nitrided oxides by using multifrequency and multitemperature charge pumping technique in conjunction with the tunneling model of trapped charges. Nitrided oxide is widely used to improve the reliability of nanoscale MOSFETs because it can decrease the degradation of gate oxide due to the generation of traps therein. Based on the measurement, the optimum nitrogen concentration in such typical nitrided process is discussed in correlation with the gate oxide thickness for nanoscale CMOSFETs.

Novel test structure is proposed for on-chip evaluation of the crosstalk-induced variation of coupling capacitance in multi-fanout and global interconnect lines. Then, it is experimentally shown that the crosstalk-induced variation of coupling capacitance, /spl Delta/C/sub C/ can be larger than the static coupling capacitance, C/sub C/ for both multi-fanout and global interconnect using the novel on-chip test structures. HSPICE simulation is performed to confirm the experimental data.

In this study, a highly thermal immune Ni–germanosilicide utilizing a 1%-nitrogen-doped nickel and a Co/TiN double capping layer is proposed for nano-scale complementary metal oxide semiconductor field effect transistors (CMOSFETs). It is shown that thermal stability of Ni–germanosilicide is improved a lot by the nitrogen incorporation in Ni–germanosilicide film using the 1%-nitrogen-doped nickel target and Co/TiN double capping layer. Even after the post-silicidation annealing at 600 °C for 30 min, low resistivity Ni–germanosilicide can be achieved. It is believed that the nitrogen atoms in 1%-nitrogen-doped nickel are incorporated in the Ni–germanosilicide during silicidation and formed a nitride compound at the grain boundaries of Ni–germanosilicide and the Ni–germanosilicide/SiGe interface.

In this paper, reliability (HCI, NBTI) and device performance of nano-scale CMOSFETs with different channel stress were investigated. It was shown that NMOS and PMOS performances were improved by tensile and compressive stress, respectively, as well known. It is shown that improved device performance is attributed to the increased mobility of electrons or holes in the channel region. However, reliability characteristics showed different dependence on the channel stress. Both of NMOS and PMOS showed improved hot carrier lifetime for compressive channel stress. NBTI of PMOS also showed improvement for compressive stress. It is shown that generation at the interface of has a great effect on the reliability. It is also shown that generation of positive fixed charge has an effect in the NBTI. Therefore, reliability as well as device performance should be considered in developing strained-silicon MOSFET.

In this paper, novel test patterns and on-chip data are presented to indicate that the variation of coupling capacitance, by crosstalk can be larger than static coupling capacitance, Cc. It is also shown that is strongly dependent on the phase of aggressive lines. for anti-phase crosstalk is always larger than Cc while for in-phase crosstalk is smaller than Cc. HSPICE simulation shows good agreement with the measurement data.