— This paper presents a practical technique that uses Ping's interleave(r)-division multiple access and single-user decoding to provide uncoordinated access for a family of binary-input binary-output multiple-access channels (MACs) including the OR-MAC where users' binary transmissions are combined with the logical OR operation. Information theoretic calculations provide the achievable sum-rates and optimal ones densities for these MACs. Because the required ones densities are significantly less than 50%, new nonlinear trellis code analysis and design techniques are introduced to provide the needed codes. Union bound techniques that predict the performance of these codes are also presented. Simulation results and a working FPGA implementation verify the performance and feasibility of the proposed nonlinear codes and overall multiple access scheme.

In this paper we propose an architecture design methodology to optimize the throughput of MD4-based hash algorithms. The proposed methodology includes an iteration bound analysis of hash algorithms, which is the theoretical delay limit, and Data Flow Graph transformations to achieve the iteration bound. We applied the methodology to some MD4-based hash algorithms such as SHA1, MD5 and RIPEMD-160. Since SHA1 is the algorithm which requires all the techniques we show, we also synthesized the transformed SHA1 algorithm in a 0.18 μm CMOS technology in order to verify its correctness and its achievement of high throughput. To the best of our knowledge, the proposed SHA1 architecture is the first to achieve the theoretical throughput optimum beating all previously published results. Though we demonstrate a limited number of examples, this design methodology can be applied to any other MD4-based hash algorithm.

Though it promises high bandwidths, the optical medium is not popular in local area networks. This is because current optical networks do not offer the ease of use and setup that an uncoordinated multiple access network such as Ethernet offers. In this paper, we propose a novel nonlinear trellis code designed for multiple access among uncoordinated nodes in an optical communications system. This code has been shown to have an efficiency of 30%. We have implemented the codes on Xilinx FPGA's for a 6 user optical system, transmitting data on a single wavelength. The above system was set up using commercial off-the-shelf components and we demonstrated BER <10-9of for three users, each running at a channel rate of 2 Gbps. Demonstration of this system required the design of new channel codes, architectural optimizations for the implementation of the channel codes for high speed with limited resources and electrical/optical optimizations to realize the optical channel.

The hash algorithm forms the basis of many popular cryptographic protocols and it is therefore important to find throughput optimal implementations. Though there have been numerous published papers proposing high throughput architectures, none of them have claimed to be optimal. In this paper, we perform iteration bound analysis on the SHA2 family of hash algorithms. Using this technique, we are able to both calculate the theoretical maximum throughput and determine the architecture that achieves this throughput. In addition to providing the throughput optimal architecture for SHA2, the techniques presented can also be used to analyze and design optimal architectures for some other iterative hash algorithms.

In this paper, the authors analyze the theoretical delay bound of the SHA-1 algorithm and propose architectures to achieve high throughput hardware implementations which approach this bound. According to the results of FPGA implementations, 3,541 Mbps with a pipeline and 893 Mbps without a pipeline were achieved. Moreover, synthesis results using 0.18mum CMOS technology showed that 10.4 Gbps with a pipeline and 3.1 Gbps without a pipeline can be achieved. These results are much faster than previously published results. The high throughputs are due to the unfolding transformation, which reduces the number of required cycles for one block hash. The authors reduced the required number of cycles to 12 cycles for a 512 bit block and showed that 12 cycles is the optimal in our design

One of the pillars of trust-worthy computing is process isolation, the ability to keep process data private from other processes running on the same device. While embedded operating systems provide isolation for the software part of these processes, there is no commonly accepted isolation mechanism for the hardware resources. As a result, systems may remain vulnerable to hardware-based attacks. This paper presents a secure coprocessor interface that extends the concept of process isolation into reconfigurable hardware. In the resulting coprocessor design, context information for different processes concurrently accessing the coprocessor is physically kept private. The coprocessor interface can handle context switches between different processes without assistance of the operating system. Because of this, reconfiguration of computation units can occur independent of the main processor. Moreover, it does so with greater efficiency than what is possible using software only.

This paper presents nonlinear trellis codes that produce codewords with a relatively low density of ones. These trellis codes are designed specifically for the Z-Channel that arises in a multipleuser optical channel with non-coherent combining, when the other users are treated as noise. In conjunction with interleaver-division multiple access, these trellis codes provide a relatively low complexity solution for uncoordinated access in the optical multiple-user environment. Also, a union bound technique that predicts the performance of these codes is presented. An implementation on an FPGA is described and results are shown.

ÿ ÿ Herwin Chan, Patrick Schaumont and Ingrid Verbauwhede {herwin, schaum, ingrid} @ ee.ucla.edu Electrical Engineering Department University of California, Los Angeles ÿ ÿ ÿ AbstractThis paper describes an implementation of an AES coprocessor interface that provides greater security between software threads running on a single microprocessor. Each of these threads may use the AES core for encryption or decryption in several different modes of operation. The data from different threads is kept physically separate, which offers security by preventing information leakage across threads. The data sets are supported with a group of small programmable hardware controllers to handle the calculation of each software thread.

This paper presents nonlinear trellis codes that produce codewords with a relatively low density of ones. These trellis codes are designed speci- cally for the Z-Channel that arises in a multiple- user optical channel with non-coherent combining, when the other users are treated as noise. In con- junction with interleaver-division multiple access, these trellis codes provide a relatively low com- plexity solution for uncoordinated access in the optical multiple-user environment. Also, a union bound technique that predicts the performance of these codes is presented. An implementation on an FPGA is described and results are shown.