This paper presents a ring-oscillator (RO) based true random number generator (TRNG) that improves a 97.54% bias reduction, achieving a high entropy per bit of 0.986 (NIST SP 800-90B IID-track) without post-processing at 4 Mbps. Enabled by a simple yet novel bias-mitigation method, the proposed TRNG occupies only $80.198 \text{um}^{2}$.

Security is increasingly more important in designing chips and systems based on them, and the International Solid-State Circuits Conference (ISSCC), the leading conference for presenting advances in solid-state circuits and semiconductor technology, is committed to hardware security by establishing the security subcommittee since 2024. In the past two years, the authors of this paper reviewed submissions as members of the Security Subcommittee, a part of International Technical Program Committee (ITPC). This paper aims to encourage high-quality submissions to grow this field in the overall scope of the ISSCC.

This paper presents the Samsung TRNG system IP, which provides a root of trust for secure SoC architectures. With over 15 years of mass-production experience, the TRNG system IP offers reliable operation and robust security against various attacks, meeting certifications such as NIST ESV (Entropy Source Validation) and CC (Common Criteria) at a high EAL (Evaluation Assurance Level). The IP is designed to meet the demanding requirements of mathematical modeling, runtime detection mechanisms to ensure entropy quality, and resistance against fault attacks. Furthermore, it complies with ISO 26262 ASIL-D for automotive applications, ensuring the highest level of safety and security in connected vehicles and other critical systems.

This paper presents a physically unclonable function (PUF) design implemented solely with standard cells. The proposed PUF extracts entropy from process mismatches in the threshold voltages $(\mathrm{V}_{\text{th}})$ of inverting cells. An $\text{additional}\mathrm{V}_{th}$ tilting scheme supports efficient PUF enrollment by screening potentially unstable responses, requiring processing only at nominal voltage/temperature (V/T) conditions. The PUF design has been implemented in 3nm GAA and 8nm FinFet technology nodes and verified on test chips across various process corners. The average bit error rate (BER) at the worst process-voltage-temperature (PVT) corner is as low as 0.3127%, enabling stable PUF key generation with a key error rate (KER) below $5.5\times 10^{-20}$, applying error corrections. Among the additional features, the power-gating scheme reduces the impact of bias-temperature instability (BT1) aging on PUF cells, the balanced sampler reduces the risk of side-channel information leakage, and laser-attack detector cells are strategically positioned near the sampling flip-flops. The PUF design, implemented solely with the standard cell library, offers significant advantages for porting to other technology nodes, while the efficient enrollment procedure reduces time and resource demands during the electrical die sorting (EDS) process for mass testing.

This letter presents a high-performance True Random Number Generator (TRNG) based on Self-Timed Ring (STR), showing robust tolerance to PVT variations. The evaluations were performed over 320 chips (64 chips per process corner of nn, ff, ss, sf, and fs) across 3 voltages (0.75V, 0.75V +/- 10%) and 3 temperatures (-40degree celsius, 25degree celsius, and 150 degrees C). All 320 test chips demonstrated stable random generation at 60Mb/s over all test combinations without a single failure. The verification utilized a TRNG BIST, ensuring a minimum of 0.5 min-entropy per bit. Moreover, a mathematical model for the proposed TRNG is developed to derive the throughput and the entropy of the random output.

True Random Number Generators (TRNGs) are essential for security protocols and cryptographic algorithms, employing random numbers in a variety of cryptographic applications pursuing data integrity, confidentiality, and authenticity. They often require high-throughput capabilities for scenarios such as financial transactions, real-time data processing, and large-scale communications. In addition, keeping the stable quality of randomness in terms of entropy per bit across wide PVT variations is an essential requirement. Otherwise, an attacker can take advantage of it, causing a serious security vulnerability.

Physically unclonable functions are the most secure technology to keep a static cryptographic key in a device due to its unclonable and volatile properties, where PUF responses disappear when the power is off. These make a PUF-based key is intrinsically secure against reverse engineering. Though the PUF itself is secure, its integration into a system must be carefully designed to keep its security. This paper presents SAMPUF™ design approach and its integration with security systems.

Protection of information is of paramount importance in today's digital age. Physically Unclonable Functions (PUFs) are considered a secure method for security key generation because they generate responses that exist only during operation. A challenge regarding the use of PUFs is to achieve high reliability. Therefore, various schemes such as temporal majority voting [2], [3], [4], spatial majority voting [1], BCH [1], [3], and burn-in [3], are applied to improve the stability of the responses. While a recent paper proposed a method of oxide-break to achieve zero error [5], it is controversial if it is a real PUF since the response value (i.e. the status of the oxide-break) can be observed by reverse engineering. Automotive is an application area where reliability is particularly important, as failures may lead to critical accidents. To satisfy the reliability of AEC-Q100 Grade 1, functionality under -40-to-125°C in ambient temperature (Ta) must be guaranteed, even considering the aging effects on a chip. To satisfy IS026262 ASIL-B, the fault coverage must be over 90%. This paper shows a PUF satisfying both AEC-Q100 Grade 1 and IS026262 ASIL-B, where our testing temperatures cover -40-to-150°C in junction temperature (Tj) to compensate for the increased thermal heat within the SoC package.

Physically unclonable function (PUF) circuits are for generating unique secure keys or chip IDs based on intrinsic properties of each chip itself [1-2]. PUFs are a step forward to improve the security level compared to traditional NVM (non-volatile memory) solutions (FUSEs, EEPROM/FLASH, etc.) because they resolve security issues, such as active data-probing, transferring the security key from outside, etc. Since the MOSFET mismatch (e.g. size, doping concentration, mobility and oxide thickness) due to process variations cannot be fully controlled, PUFs, which are based on such phenomena, cannot be replicated. Unfortunately, the PUF output is erroneous by nature, as caused by thermal noise, voltage/temperature influence, aging effects, etc. The stability issue must be overcome since standard security applications, such as data encryption and digital signatures, have zero error-tolerance. In this work, a PUF structure based on the threshold voltage (Vth) difference of inverting logic gates is presented, which is implemented for secure 24b key generation in a 45nm smart card chip. The key is used as part of an encryption key and achieves an error rate as low as 2.01×10-38. The PUF system is also scalable for a larger key size.

Since the introduction of the concept of grouping proofs by Juels, which permit RFID tags to generate evidence that they have been scanned simultaneously, various new schemes have been proposed. Their common property is the use of symmetric-key primitives. However, it has been shown that such schemes often entail scalability, security and/or privacy problems. In this article, we extend the notion of public-key RFID authentication protocols and propose a privacy-preserving multi-party grouping-proof protocol which relies exclusively on the use of elliptic curve cryptography (ECC). It allows to generate a proof which is verifiable by a trusted verifier in an offline setting, even when readers or tags are potentially untrusted, and it is privacy-preserving in the setting of a narrow-strong attacker. We also demonstrate that our RFID grouping-proof protocol can easily be extended to use cases with more than two tags, without any additional cost for an RFID tag. To illustrate the implementation feasibility of our proposed solutions, we present a novel ECC hardware architecture designed for RFID.

The concept of grouping proofs has been introduced by Juels to permit RFID tags to generate a verifiable proof that they have been scanned simultaneously, even when readers or tags are potentially untrusted. In this paper, we extend this concept and propose a narrowstrong privacy-preserving RFID grouping proof and demonstrate that it can easily be extended to use cases with more than two tags, without any additional cost for an RFID tag. Our protocols rely exclusively on the use of Elliptic Curve Cryptography (ECC). To illustrate the implementation feasibility of our proposed solutions, we present a novel ECC hardware architecture designed for RFID.

The emergence of pervasive computing devices such as RFID tags raises numerous privacy issues. Cryptographic techniques are commonly used to enable tag-to-server authentication while protecting privacy. Unfortunately, these algorithms and their corresponding implementations are difficult to adapt to the extreme conditions implied by the use of RFID. The extremely limited budget for energy and area do not allow the use of traditional cryptography. In this paper, we address the risk of tracking attacks in RFID networks. Many lightweight protocols have been proposed so far that are founded on both, private- and public-key cryptosystems. We give an overview of existing solutions and discuss the latter ones in more detail. The solutions we advocate in this paper rely exclusively on Elliptic Curve Cryptography (ECC). We describe several authentication protocols that have different computational demands and accordingly different security features. To the best of our knowledge, these protocols are the first ECC-based authentication protocols which offer privacy protection against a wide-weak attacker. Compared to other RFID schemes proposed in the literature, our protocols remain light-weight in terms of area and computation time, while still achieving the required security and privacy properties.

The emergence of pervasive computing devices has raised several privacy issues. In this paper, we address the risk of tracking attacks in RFID networks. Our contribution is threefold: (1) We repair three revised EC-RAC protocols of Lee, Batina and Verbauwhede and show that two of the improved authentication protocols are wide-strong privacy-preserving and one wide-weak privacy-preserving; (2) We present the search protocol, a novel scheme which allows for privately querying a particular tag, and proof its security properties; and (3) We design a hardware architecture to demonstrate the implementation feasibility of our proposed solutions for a passive RFID tag. Due to the specific design of our authentication protocols, they can be realized with an area significantly smaller than other RFID schemes proposed in the literature, while still achieving the required security and privacy properties.

Due to its cryptographic and operational key features such as the one-way function property, high speed and a fixed output size independent of input size the hash algorithm is one of the most important cryptographic primitives. A critical drawback of most cryptographic algorithms is the large computational overhead. This is getting more critical since the data amount to process or communicate is increasing a lot. In many cases, a proper use of the hash algorithm reduces the computational overhead. Digital signature generation and the message authentication are the most common applications of the hash algorithms. The increasing data size also motivates hardware designers to have a throughput optimal architecture for a given hash algorithm. In this chapter, some popular hash algorithms and their cryptanalysis are briefly introduced, and a design methodology for throughput optimal architectures of MD4-based hash algorithms is described in detail.