Despite the fact that retiming circuits have a large potential (especially in automatically synthesized circuits from higher-level descriptions) it has not been widely included in the current design methodologies. One of the main problems is finding an equivalent initial state for the retimed logic. In this paper we introduce a new reverse retiming algorithm which will find a retiming for a given cycle time, if one exists. This new algorithm minimizes the effort required to find equivalent initial states and reduces the chance that the network needs to be modified to find an equivalent initial state. This algorithm is the kernel of a new efficient retiming method, which searches for optimal retimings preserving the initial state condition.

In this paper we deal with the detection of functional faults in RAM's. We present a fault model which consists of decoder faults and memory array faults. We rectify and extend previous definitions of decoder faults, and we refine previous definitions of two coupling faults. Three test sequences of length 9N, 13N and 17N are presented with proofs of increasing detection capabilities. Our test sequence of length 17N is capable of detecting all combinations of faults in our model.

A Decoded INstruction Cache (DINC) serves as a buffer between the instruction decoder and the other instruction-pipeline stages. In this paper we explain how techniques that reduce the branch penalty based on such a cache, can improve CPU performance. We analyze the impact of some of the design parameters of DINCs on variable instruction-length computers, e.g., CISC machines. Our study indicates that tuning the mapping function of the instructions into the cache, can improve the performance substantially. This tuning must be based on the instruction length distribution for a specific architecture. In addition, the associativity degree has a greater effect on the DINC's performance, than on the performance of regular caches. We also discuss the difference between the performance of DINCs and other caches, when longer cache lines are used. The results presented were obtained by both analytical study and trace-driven simulations of several integer UNIX applications.

A Decoded Instruction Cache improves the performance of pipalined computers. In order to build the cache, several non-obvious decisions have to be taken. This work shows the benefits of using such a cache and studies the behavior of a Decoded Instruction Cache in order to find the best structure at a given cost.