The introduction of assembly programming is an important step in the education of computer engineers, as it provides a smooth transition from high level programs, developed in prior courses, to low level programs. This transition aims at improving the understanding of how programs are executed by computers, presenting concepts such as instructions, registers, data representation, execution mode privileges, and external devices. Such concepts are fundamental for later courses in the computer systems field, for instance, computer architecture, operating systems, computer networks, cybersecurity, and compiler design. Given the practical coursework intrinsic to computer systems courses, a platform that enables the development of such activities in a hassle-free manner regarding setup and use, can enrich the learning process of students. In this work, we present a set of teaching materials for assembly programming that consists of an extensible web-based simulator, its manual, and an exercise book. The chosen instruction set architecture (ISA) was RISC-V, as it is an open ISA, has a simple and reduced set of instructions, and has seen rising popularity in both academia and industry. The materials are suitable for either introductory courses with simple assembly programming activities or more advanced courses on the topic that may cover peripheral programming, system calls and interrupt handling.
This paper presents our recent experiences of teaching the "Real-time Embedded Systems Design" course by applying a Real-Time Operating System (RTOS) called Eclipse ThreadX. It transitioned to free, open-source software from Microsoft Azure RTOS in 2023. This paper mainly covers how we adopted ThreadX as a real-world RTOS example in lab sessions, including lab tutorials, programming exercises, lab equipment setup, and course projects. Unlike real-time systems courses for computer science majors, we focus on teaching engineering majors (EE and CE) students the design and application development of real-time embedded systems from the practitioner's point of view. This real-time embedded systems design course is for senior and graduate students majoring in electrical and computer engineering. After completing this course, students are expected to demonstrate the ability to design and develop real-time systems for microcontroller-based embedded applications (i.e., STMicroelectronics IoT Discovery Kit). Project-based learning and hands-on learning are the primary teaching approaches employed in this course. Based on our teaching experiences. ThreadX is an RTOS with rich and unique features and utility tools for teaching real-time systems design and developing cloud-based IoT applications. This paper also summarizes our nearly 10 years of experience in teaching FreeRTOS, another widely used open source RTOS, and compares it with ThreadX. Our latest experiences show that combining Eclipse ThreadX and FreeRTOS can yield synergistic benefits in terms of teaching effectiveness.
Cache coherence is a core topic in a parallel computer architecture course. The choice of protocol and other cache design parameters influences the performance of software that shares data across processors, so an in-depth understanding of them is a must-have. This paper discusses an L1 cache simulator that can simulate both SMP and DSM protocols. Students are given the skeleton of a simulator and an implementation of one or more protocols. They are asked to construct implementations of additional protocols, and then measure their performance on traces from standard benchmark suties. The simulator also offers an interactive mode that reports performance metrics after each individual memory access as the student enters them. This simulator is built in C++ and designed with modularity and extensibility in mind, enabling and encouraging further development to add support for more protocols. The paper describes the structure of the simulator, the coherence protocols that have been implemented, as well as sample assignments.
Understanding how computer programs interact with memory caches is key to optimizing system performance. Our paper introduces the Visual Memory Simulator (VMS), a user-friendly tool that visualizes caches' temporal and spatial utilization. VMS has three components: cache simulator, visualization backend, and GUI. It inputs either a C program or a memory trace. VMS also provides a tracer so users can generate their memory traces. VMS is useful for students to understand cache concepts and researchers to identify memory bottlenecks. VMS provides an intuitive interface where researchers can input code or traces and instantly see cache utilization. Dynamic visualizations help identify optimization possibilities by showing how programs interact with the cache hierarchy. Moreover, VMS allows exploring cache behavior in different settings, giving researchers insight into the effects of various configurations and access patterns.
This paper introduces Ptah, a project-based learning framework for teaching computer architecture by engaging students in designing and deploying NLP-controlled drones powered by edge computing and Kubernetes orchestration. Ptah provides a hands-on educational experience by integrating lightweight NLP models such as BERT into containerized microservices running on modular edge hardware-including Turing Pi 2.5 with Jetson Orin NX, TRK1 with 32 GB RAM, and Turing Pi 2.0 with Jetson Nano and Raspberry Pi Compute Module 4-coordinated via ClusterHAT 2.0 and DeskPi Super6C with Pi Zero 2 W nodes. As students issue spoken commands like "hover," "move forward," or "return home," they witness live end-to-end latencies (1 000-3 000 mu s) as inputs flow through a scalable microservice pipeline orchestrated by K3s and RabbitMQ. Crucially, Ptah exposes L1/L2 cache miss rates and TLB-miss behavior via simple perf and /proc/pid/pagemap experiments on the Orin NX, linking textbook CPU/memory abstractions to real hardware measurements. Learners gain intuitive insights into core architectural concepts-CPU scheduling, I/O systems, memory access, parallelism, and system bottlenecks-through real-time feedback and visualization of how high-level AI-driven commands propagate through hardware and software layers. Deployed in the Reconfigurable Space Computing Lab and integrated into NASA MINDS and DoD-funded studies, Ptah demonstrates a replicable, future-ready model for bridging theory and practice in computer architecture education.
This paper introduces SCOoOTER, an open-source, highly-configurable RISC-V processor designed for courses on advanced processor architecture and design, reaching from architecture down to chip implementation. SCOoOTER offers students the opportunity to explore and extend processor functionality through a modular architecture and a wide range of configuration options, incorporating advanced architectural concepts such as dynamic instruction scheduling, speculative execution, branch prediction, and multithreading, providing a rich environment for hands-on learning. The processor is integrated with several educational tools, such as automated testing suites, debugging tools, built-in performance evaluation, and FPGA and ASIC design generation, enabling students to efficiently explore and validate different design decisions down to the physical layer. Except for FPGA synthesis and (optional) functional verification, SCOoOTER exclusively relies on freely available, open-source tools to ensure accessibility and avoid cumbersome NDAs, high per-seat EDA licensing costs, and the associated organizational overhead. Our evaluation shows that SCOoOTER achieves competitive performance to the CVA6 application-class processor, while also being more accessible to novice users due to its education-focused documentation and extensive integration and evaluation tools. Furthermore, SCOoOTER is aligned with widely-used textbooks on processor design, making it an ideal platform for students to learn and apply modern processor architecture concepts. Additionally, we highlight the potential for students to enhance SCOoOTER by implementing additional functionalities, which serves as a hands-on introduction to modern processor design and optimization techniques. Overall, SCOoOTER serves as a powerful educational platform that enables students to engage deeply with processor architecture at all abstraction levels and gain experience relevant to both research and industry practices in processor design.
System-on-Chip Platforms is an advanced course in the computer engineering curriculum at Columbia University that focuses on system-level design principles to expose students, both theoretically and practically, to the main challenges of SoC engineering. The course is divided into two complementary (principles and practice) tracks. In recent years, we have revamped the practice track to give students hands-on experience with SoC design and programming. A key component of this effort is the introduction of object-oriented high-level synthesis, which enables students to acquire the skills necessary to design their own hardware accelerators. In the collaborative final project, students optimize an accelerator and combine it with accelerators designed by other students to create a complete SoC for a target application. The project is based on open-source hardware and can be replicated at other universities.
Deep Learning kernels, such as general matrix multiplications (GEMMs), exhibit high data-reuse or operations per byte that help in improving their performance on hardware. Yet young architects often struggle to internalize the benefits of data reuse. In this work, we introduce an intuitive water-flow analogy for a simple memory-compute model to clarify how bandwidth, on-chip memory, data reuse and compute throughput interact to determine GEMM performance. In this analogy, DRAM is the tank; the memory controller is a tap with limited flow and latency; SRAM is the bucket; compute units are the dish-washer. We also illustrate the role of data reuse through worked out examples, showing compute- and memory- bound scenarios in roofline performance model, as well as latency-bound scenario. By grounding architectural ideas in physical world scenario, our water-flow analogy helps in longer retention of concepts related to data reuse and memory hierarchy. We also provide ready-to-use slides for its easy adoption in courses1.
FREESS is a free, interactive simulator that illustrates instruction-level parallelism in a RISC-V-inspired superscalar processor. Based on an extended version of Tomasulo's algorithm, FREESS is intended as a hands-on educational tool for Advanced Computer Architecture courses. It enables students to explore dynamic, out-of-order instruction execution, emphasizing how instructions are issued as soon as their operands become available. The simulator models key microarchitectural components, including the Instruction Window (IW), Reorder Buffer (ROB), Register Map (RM), Free Pool (FP), and Load/Store Queues. FREESS allows users to dynamically configure runtime parameters, such as the superscalar issue width, functional unit types and latencies, and the sizes of architectural buffers and queues. To simplify learning, the simulator uses a minimal instruction set inspired by RISC-V (ADD, ADDI, BEQ, BNE, LW, MUL, SW), which is sufficient to demonstrate key pipeline stages: fetch, register renaming, out-of-order dispatch, execution, completion, commit, speculative branching, and memory access. FREESS includes three step-by-step, illustrated examples visually demonstrating how multiple instructions can be issued and executed in parallel within a single cycle. Being open source, FREESS encourages students and educators to experiment freely by writing and analyzing their own instruction-level programs and superscalar architectures.
Traditional educational approaches often struggle to provide personalized and interactive learning experiences at scale. In this paper, we present SocratiQ, an AI-powered educational assistant that addresses this challenge by implementing the Socratic method through adaptive learning technologies. The system employs a novel Generative AI-based learning framework that dynamically creates personalized learning pathways based on student responses and comprehension patterns. We provide an account of the core design elements of SocratiQ, practical considerations for its deployment, and user feedback on its effectiveness. Although our implementation focuses on machine learning systems education, the integration approaches we present can inform similar efforts across STEM fields. Through this work, our goal is to advance the understanding of how generative AI technologies can be designed and systematically incorporated into educational resources.
Given that most CS students, especially at liberal arts colleges, lack engineering or logic design experience, we employ visualization in our computer architecture course to expedite student learning. By having students design and learn visually, students developed a deeper understanding and appreciation of computer architecture. Within a single semester, the course equips students with the skills to engage in innovative computer architecture research. We describe the course materials, student projects, and undergraduate research. By combining visualization with experiential learning, we broaden participation and encourage undergraduate research in computer architecture. The course materials will be made publicly available.
A new tool called Visceral VCD was utilized to replace FPGA hardware during the pandemic. Its functionality was proven utilizing multiple projects in a digital logic course. The pedagogy of the assignments is discussed in detail, as well as how the use of Visceral VCD allowed electrical and computer engineering students to complete all coursework remotely during quarantine. Use of this tool was continued after quarantine restrictions eased due to its effectiveness. Visceral VCD can be used in place of hardware for multiple hardware description languages and FPGA development environments.
Computer architecture students today arguably do not have as close a connection to energy as they do to performance. Specifically, they are not trained to reason about energy in a quantifiable way. Architecture students are taught that performance and energy are considered equally important. However, most course material focuses on a performance-driven narrative, meaning that students learn about processors, memories, networks, and systems with a strong sense of the performance implications, but with little intuition for the energy implications. On the other hand, VLSI students concretely learn about energy, but they are immersed in a world of gates and transistors and do not connect their understanding about energy back up to the abstraction of SoC-level components. How can we bridge this gap to enable architecture students to reason about the energy implications of hardware design concepts, directly within a computer architecture class? In this work, we attempt to mitigate these challenges by introducing a teaching methodology that integrates energy into pipeline diagrams. We include examples of specific classroom tools including the representation of an energy map, and we show how pipeline diagrams augmented with an energy map can enable first-order quantitative comparisons of performance, energy, and power across different design points. The approach is simple enough for lecture, in-class activities, and in exams. We hope this approach can train future students in thinking from first principles in evaluating performance-energy tradeoffs.
Computer architecture is primarily studied through simulation. Most existing simulators are either comprehensive research tools, or ones targeting a single area within computer architecture. CADSS is an open source computer architecture simulator that can support simulations written in multiple languages across a variety of areas of computer architecture, either individually or combined together. It is designed to support student learning, as well as assessment by instructors.
This paper describes the computer architecture content in Dive into Systems, our free, online textbook that introduces a broad range of computer systems topics. Dive into Systems assumes only a CS1 background of the reader, and includes numerous examples and illustrations to foster a reader’s understanding of its content. Our textbook is designed to be used as a primary textbook for a range of courses that introduce computer systems and computer architecture topics. It also serves as a supplementary text in upper-level undergraduate and graduate level courses to provide background material on computer architecture, systems, and parallel computing. In addition to presenting the details about our book’s coverage of computer architecture topics, we also discuss the overarching themes of our textbook and our motivations for writing a free online textbook to introduce computer systems topics. Our book is currently used by more than 45 institutions in a wide range of courses, including undergraduate computer architecture courses.
Scientists, engineers, and researchers leverage high-performance computing (HPC) systems to perform complex computations and process large amounts of data. Designing, developing, and operating HPC systems have a steep learning curve, thus making it crucial to train a highly skilled and knowledgeable workforce in order to keep up with the rapidly evolving field, drive innovation, and meet the increasing demand for HPC across various sectors. Limited access to HPC educational resources is the main deterrent to training HPC talent. This paper addresses two primary culprits for the limited access: the high cost of production systems and the lack of realistic full-stack HPC training. Cutting-edge hardware is usually expensive and requires specialized facilities. Moreover, large HPC facilities typically discourage experimenting with the systems since they run production computation workloads and require minimal disturbance. Furthermore, HPC training often does not reflect the scale or complexity of production systems. This lack of realistic training support makes education in this area particularly difficult and ineffective. This paper proposes an educational framework for HPC that includes the development of a low-cost and flexible platform design for users in diverse fields. It allows study and experimentation with multiple realistic elements involved in a production HPC ecosystem. DEMAC, the Delaware Modular Assembly Cluster, is a set of 3D-printable frames designed to house embedded systems and auxiliary systems in a way that emulates HPC platforms. The teaching framework focuses on practical training as an education model in which learners reinforce theoretical knowledge with hands-on experience. If successful, this effort will contribute fundamentally to scientific research, technological advancements, HPC workforce development, and economic growth.
The traditional model of assigning textbook problems for homework is endangered by the ability of students to find answers to almost any published problem on the web. An alternative is a dual-submission approach, where students submit their work, then receive the solutions, and submit a second metacognitive reflection, explaining any errors they made. Students’ scores can depend on the quality of their second submissions alone or the combined quality of their first and second submissions. We tried this approach in a class on parallel computer architecture. We report students’ personal experience based on their questionnaires responses. In addition, we quantitatively compare students’ performance on test questions related to dual-submission homework against their performance on other questions and previous semesters’ student performance on similar questions. Students overwhelmingly preferred this approach and thought they learned more from it, but evidence about whether it improved their learning was inconclusive. We also analyze the continued viability of this approach in the era of large language models.
With the continuous expansion of the DNN accelerator scale, inter-layer scheduling, which studies the allocation of computing resources to each layer and the computing order of all layers in a DNN, plays an increasingly important role in maintaining a high utilization rate and energy efficiency of DNN inference accelerators. However, current inter-layer scheduling is mainly conducted based on some heuristic patterns. The space of inter-layer scheduling has not been clearly defined, resulting in significantly limited optimization opportunities and a lack of understanding on different inter-layer scheduling choices and their consequences. To bridge the gaps, we first propose a uniform and systematic notation, the Resource Allocation Tree (RA Tree), to represent different inter-layer scheduling schemes and depict the overall space of inter-layer scheduling. Based on the notation, we then thoroughly analyze how different inter-layer scheduling choices influence the performance and energy efficiency of an accelerator step by step. Moreover, we show how to represent existing patterns in our notation and analyze their features. To thoroughly explore the space of the inter-layer scheduling for diverse tiled accelerators and workloads, we develop an end-to-end and highly-portable scheduling framework, SET. Compared with the state-of-the-art (SOTA) open-source Tangram framework, SET can, on average, achieves 1.78× performance improvement and 13.2% energy cost reduction simultaneously. Moreover, the SET framework will be open-sourced.
Memory disaggregation is a promising solution to scale memory capacity and bandwidth shared by multiple server nodes in a flexible and cost-effective manner. DRAM power consumption, which is reported to be around 40% of the total system power in the datacenter server, will become an even more serious concern in this high-capacity environment. Exploiting the low average utilization of DRAM capacity in today's datacenters, it is appealing to put unallocated/cold DRAM ranks into a power-saving mode. However, the conventional DRAM address mapping with fine-grained interleaving to maximize rank-level parallelism is incompatible with such rank-level DRAM power management techniques. Furthermore, existing DRAM power-saving techniques often require intrusive changes to the system stack, including OS, memory controller (MC), or even DRAM devices, to pose additional challenges for deployment. Thus, we propose DRAM Translation Layer (DTL) for host software/MC-transparent DRAM power management with commodity DRAM devices. Inspired by Flash Translation Layer (FTL) in modern SSDs, DTL is placed in the CXL memory controller to provide (i) flexible address mappings between host physical address and DRAM device physical address and (ii) host-transparent memory page migration. Leveraging DTL, we propose two DRAM power-saving techniques with different temporal granularities to maximize the number of DRAM ranks that can enter low-power states while provisioning sufficient DRAM bandwidth: rank-level power-down and hotness-aware self-refresh. The first technique consolidates unallocated memory pages into a subset of ranks at deallocation of a virtual machine (VM) and turns them off transparently to both OS and host MC. Our evaluation with CloudSuite benchmarks demonstrates that this technique saves DRAM power by 31.6% on average at a 1.6% performance cost. The hotness-aware self-refresh scheme further reduces DRAM energy consumption by up to 14.9% with negligible performance loss via opportunistically migrating cold pages into a rank and making it enter self-refresh mode.
Although smell is arguably the most visceral of senses, olfactory computing has been barely explored in the mainstream. We argue that this is a good time to explore olfactory computing as driver applications are emerging, sensors are dramatically better, and nontraditional form factors that would be required to support olfactory computing have widespread acceptance. Through a comprehensive review of literature, we identify the key algorithms needed to support a wide variety of olfactory computing tasks. We profiled these algorithms on existing hardware and identified several characteristics, including the preponderance of fixed-point computation, linear operations, and real arithmetic; a variety of data-memory requirements; and opportunities for data-level parallelism. We propose Ahromaa, a heterogeneous architecture for olfactory computing that targets power- and energy-constrained olfactory computing workloads, and evaluate it against the baseline architectures of a microcontroller unit (MCU), coarse-grained reconfigurable array, and an MCU with packed single instruction, multiple data.
