The relationship between the microstructure of silicon nitride and its sensitivity to moisture was studied. The effectiveness of Si-H rich and N-H rich silicon nitride layers was measured under attack from water in vapor and liquid states. For water vapor attack, samples are exposed to vapor at 85 °C with a relative humidity of 85% during 1600 hours; for liquid water attack, samples are dipped in water at 60, 85 and 100 °C for 200 hours. The water resistance of the Si-H rich and N-H rich silicon nitride layers was evaluated by measuring: (i) the thickness of the silicon dioxide formed after their oxidation with water vapor, (ii) the rate of dissolution of the silicon nitride in liquid water and (iii) the corresponding activation of energy. This evaluation was performed by coupling spectroscopic ellipsometry, infra-red and X-ray photoelectron spectrometry analyses. The results revealed that for Si-H rich layer, 10 nm of silicon dioxide was formed during the water vapor attack; for liquid water attack, a high activation energy (0.88 eV) and a low dissolution rate were observed regardless of the water temperature. For N-H rich layers, approximatively 6–8 nm of silicon dioxide was formed and a low activation energy (0.64 eV) with a high dissolution rate were observed. All of these observations lead to the conclusion that the N-H rich layers could be less resistant to moisture because the isoelectronic relationship between Si2N-H and −H2O+ facilitated their deterioration in water. Moreover, a higher rate of nanoporosity for N-H rich layers than Si-H rich layer could complete this hypothesis.

Au cours d’etudes par profilage XPS de la composition de films de Nichrome, d’importantes variations sur la quantite d’oxygene apres erosion ont ete observees. Ces variations ne dependent pas de l’etat d’oxydation de la couche superficielle mais de l’intervalle de temps entre l’erosion et l’acquisition du spectre O1s. L’etude a mis en evidence que la teneur en oxygene augmente des la premiere minute apres erosion et continue sur 6 heures. L’apparition de composantes a haute energie sur les pics Cr2p montre une oxydation concomitante du chrome.

An accurate knowledge of the phenomenon is required to develop a predictive modeling of the electro-migration failure. Thus, a hitherto unseen SEM in operand observation method is devised. The test structure with "high density" through silicon vias (TSV) is tested at 623 K with an injected current density of 1 MA/cm(2). Regular shots of micrographs inform about the voids nucleation, forced in copper lines above the TSV, and about the scenario of their evolution. A clear relation is established between voids evolution and the one of the electrical resistance. The lack of impact of test conditions on the failure mechanism is demonstrated. Finally, the impact of microstructure on the depletion mechanism is discussed. Grain boundaries are preferential voids nucleation sites and influence the voids evolution. A probable effect of grain size and crystallographic orientation is revealed. (C) 2015 Elsevier Ltd. All rights reserved.

This paper aims at determining thermomechanical stress variations induced by annealed copper filled through-silicon via (TSV) in single crystalline silicon using metal-oxide-semiconductor (MOS) rosette sensors. These eight branches sensors were specifically designed and embedded in a 65-nm CMOS technology test vehicle. An in-house four-point bending tool was employed to calibrate and to extract the six independent piezoresistive coefficients. Through the piezoresistive relations, the stress tensor was evaluated by carrying out electrical measurements on wafer splits. A finite-element approach was also adopted to evaluate numerically the stresses and the expected mobility variations induced by TSV. According to this paper, a large variation of stresses (up to 100 MPa) in the sensor area was estimated, suggesting possible sensor design improvements to better accuracy. A good agreement was obtained between numerical and experimental results, except for the orthoradial component, which was found slightly compressive experimentally. Based on a critical analysis of the experimental-numerical methodology and results detailed in this paper, guidelines are drawn to get better accuracy through the improvement of MOS size and positions as well as recommendations regarding test strategy to overcome process variability. In the longer term, such improvements should lead to the definition of a comprehensive strategy for mechanical stress probing with in situ structures in advanced semiconductor products.

Accelerated life tests on microelectronic devices are needed to estimate their degradation under severe environment. THB (Temperature Humidity Bias) [1] at 85°C and 85%RH (relative humidity) is commonly used for reliability studies. Empirical acceleration laws, used for THB test take into account the temperature change (from 22°C to 85°C), but they do not quantify its impact of the corresponding thermo-elastic stress which it adds to the residual stress in the die and of possible microstructure changes. The aim of this work is to determine the thermo-mechanical stresses induced in the active layer of a Gallium Arsenide (GaAs) chip by the THB test. They are due to the mismatch in Coefficients of Thermal Expansion (CTE) between the stack of thin film materials used as metallurgic interconnection and the intermediate dielectric layers above the active area of the chip. To estimate this stress, fist layers thicknesses measurement have been made with various techniques; second few configurations have been used to simulate heating and finally “complete” 2D Finite Element Analysis (FEA) has been performed. Elastic and thermo-physical materials data come from the literature. The results indicate compression of metal gate (Ti/Al/Au) and tensile stress concentration in the SiNx passivation layer. The outcomes is compared with THB test results from [2] and suggests that stress induced by heating must be considered to explain failure during THB test.

The presented work is part of a problematic on silicon chips electrical interconnection on inkjet-printed films. Films are printed using a silver nanoparticles (20 nm diameter) based ink. After printing, annealing is necessary to evaporate the solvent and sinter the nanoparticles. Two types of sintering methods are studied and resulting films are characterized to evaluate their mechanical (hardness and mechanical contact) and electrical properties (contact resistance and electrical resistivity). Methods used for the annealing process are the conventional oven heating and the use of ultrashort light pulses. After this annealing step, printed films have a thickness in the order of 700 nm. Depending on the sintering conditions, porous films hardness obtained by nano-indentation is comprised between 0.6 and 0.9 GPa, depending on the sample nanostructure. This hardness remains smaller than the hardness measured for films evaporated in vacuo which is as high as 1.6 GPa (1 mm thick films). The electrical contact resistance characterization is done in-situ during the nano-indentation cycle. Resulting values, comprised between 150 and 300 mO, depend on the sintering method and enlighten the impact of the film mechanical properties during the first loading steps (F < 50 mN). This study serves to optimize the technological steps towards the realization of flexible devices by printing technics (smart RFID tags, autonomous sensors, etc.).

This work aims at implementing sense structures dedicated to the determination of the electrical responses of device due to packaging and to find ways of minimizing the stress effects on typical devices. Calibration step is carried out thanks to a four-point bending machine on 4n&4p MOS rosette sensors and bandgap (BG) structure. It is combined to 3D finite element (FE) simulations with the Ansys software on two typical packages (a large and a small die). The results show significant mobility changes in distinct regions of the dies: up to -11% diminution was found on nMOS, while pMOS are boosted up to +4%. A dedicated simulation strategy is also proposed to make the bridge between the bandgap coefficients previously calibrated and the stress components. Package simulation results show variations of the output voltage around -0.35% at the central region of the large die and -0.24% for the small one. In addition, the larger the die is, the higher the variations are. In order to reduce the impact of packaging on the device shifts, parametric studies were performed on a standard package, consisting in the variation of several component features. This allowed obtaining the device shifts close to zero: nMOS→0.008%, pMOS→0.0012% and BG→10 -5 % over a large area in the middle of the die. These studies demonstrated that the effects of packaging steps at the transistor and circuit scales cannot be neglected anymore and that managing the components parameters can minimize these effects.

Ce travail est issu d’une problématique d’interconnexion électrique d’une puce en silicium sur des films minces imprimés par jet d’encre. L’impression est réalisée en utilisant une encre à base de nanoparticules d’argent de 20 nm de diamètre moyen. Après l’impression, une étape de recuit est nécessaire pour éliminer les solvants et fritter les nanoparticules. Deux types de recuit sont étudiés et les films obtenus sont caractérisés en terme de propriétés mécaniques (dureté et contact mécanique) et électriques (résistance de contact et résistivité électrique). Ces recuits sont réalisés soit dans une étuve conventionnelle soit à travers l’utilisation d’une lumière pulsée ultra-courte. L’épaisseur du film obtenu est de l’ordre de 700 nm. En fonction des conditions de recuit, la dureté des films poreux obtenus par nano-indentation varie entre 0,6 et 0,9 GPa en fonction de la nanostructure. Cette dureté reste inférieure à celle des films obtenus par évaporation sous vide qui est de 1,6 GPa (1 μm d’épaisseur). La caractérisation de la résistance électrique de contact est réalisée in-situ pendant le cycle de nano-indentation. Les valeurs obtenues, entre 150 et 300 mΩ, sont dépendantes du type de recuit utilisé, et montrent l’effet des propriétés mécaniques des films pendant les premières phases de chargement (F< 50 mN). Cette étude sert à optimiser les étapes technologiques de réalisation de dispositifs flexibles par électronique imprimée (étiquette intelligente RFID, capteur autonome, etc.).

This work deals with a methodology to evaluate residual stresses within microelectronic devices by using MOS (Metal Oxide Semiconductor) rosette stress sensors. The stress tensor was evaluated by carrying out electrical measurements on test vehicle: the bridge from electrical to stress values was ensured by the piezoresistive relations and, prior to further in-house calibration, coefficients from literature were employed. For correlation purpose, numerical simulations were performed in order to evaluate stresses induced by TSV (Through Silicon Via). In this paper, the whole framework is described, and stress fields evaluated from in-situ electrical measurements on CMOS65 rosette sensor are compared to simulated ones. Some of the ultimate targets of this work are to develop a validated framework to deeply understand TSV induced thermo-mechanical stresses and to allow design rules definitions for products reliability and transistor performances.

The recent progress in functionalized inks based on metal nanoparticles and their subsequent deposition by inkjet-printing technologies promoted the emergence of printed electronics. Such printed structures can be treated by selective sintering techniques that enable the sintering of 20 nm-nanoparticles at process temperatures compatible with flexible plastic substrates. This article discusses the various aspects related to the production of metal tracks on flexible substrates, from the deposition using direct printing technologies, to the relationship between microstructural characteristics and electrical properties of such structures for the fabrication of devices such as antennas, interconnects or electrodes.

Colloidal suspensions of nanoparticles are increasingly employed in the fabrication process of electronic devices using inkjet-printing technology and a consecutive thermal treatment. The evolution of internal stresses during the conversion of silver nanoparticle-based ink into a metallic thin-film by a thermal sintering process has been investigated by in-situ XRD using the sin2ψ method. Despite the CTE mismatch at the film/substrate interface, the residual stress in silver films (below 70 MPa) remains lower than in conventional PVD thin-films, as a result of the remaining porosity. A Warren-Averbach analysis further showed that the crystallite growth is associated with a minimization of the twin fault density and the elastic microstrain energy above 150°C. A stabilization of the microstructure and internal stress is observed above 300°C. Inkjet-printing technology thus appears as a good alternative to conventional metallization techniques and offers significant opportunities asset for interconnect and electronic packaging.

InfraRed (IR) sensor systems like night vision goggles, missile approach warning systems and telescopes have an increasing interest in decreasing their size and weight. At the same time optical aberrations are always more difficult to optimize with larger Focal Plane Arrays (FPAs) and larger field of view. Both challenges can now take advantage of a new optical parameter thanks to flexible microelectronics technologies: the FPA spherical curvature. This bio-inspired approach can correct optical aberrations and reduce the number of lenses in camera conception.Firstly, a new process to curve thin monolithic devices has been applied to uncooled microbolometers FPAs. A functional 256x320 25 mu m pitch (roughly 1cm(2)) uncooled FPA has been thinned and curved. Its electrical response showed no degradation after our process (variation of less than 2.3% on the response). Then a two lenses camera with a curved FPA is designed and characterized in comparison with a two lenses camera with a flat FPA. Their Modulation Transfer Functions (MTFs) show clearly an improvement in terms of beams dispersion.Secondly, a new process to fabricate monolithic cooled flip-chip MCT-IRCMOS FPAs was developed leading to the first spherical cooled IR FPA: with a radius of 200 mm. Other radii are achieved. A standard opto-electrical characterization at 80 K of the imager shows no additional short circuit and no mean response alteration compared to a standard IRCMOS shown in reference. Noise is also studied with a black body between 20 and 30 degrees C.

This work aims at determining thermomechanical stresses induced by annealed copper filled Through Silicon Via (TSV) in single crystalline silicon by using MOS (Metal Oxide Semiconductor) rosette sensors. These sensors were specifically designed and embedded. Through the piezoresistive relations, the stress tensor was evaluated by carrying out electrical measurements on test vehicle. The MOS stress sensors would have been needed to be calibrated: first results of the calibration were obtained however, since they were still partial, they were not used to make the bridge from electric to mechanic quantities. Experimental findings were based on the direct calculation of stresses from electrical measurements data and literature piezoresistive coefficients. In order to get only the TSV contribution and to suppress the manufacturing process variability contribution, an optimization calculation was needed. A finite element approach was also adopted to evaluate numerically the stresses induced by TSV. The stress values obtained from the optimization are in the range of the ones obtained by simulation in the sensor area. Thus, it can be stated that the methodology is relevant, and the results will be confirmed by extracting the true piezoresistive coefficients for the embedded MOS. Once calibration performed, the piezoresistive coefficients should enable getting more accurate stress values. At this stage, the quite good agreement between numerical and experimental results seems promising.

Abstract Since the early beginning of the integrated circuits, electromigration is a reliability issue of first interest. In 3-dimensional structures, electromigration is responsible for the formation of voids in lines connected to the Through Silicon Via (TSV). To our knowledge, this paper presents the first in operando electromigration experiment in a Scanning Electron Microscope (SEM) performed for 3D integration. The experimental protocol, including sample preparation and temperature regulation, is detailed. A current of 25 mA is injected in a structure heated at 350 °C for about 900 h. The evolution of voids is monitored and explained. Void growth occurs step by step, so that the microstructure may be assumed to play a major role in the depletion mechanism. The behavior of the electrical resistance is analyzed using the SEM micrographs.

The effect of thermal profile on microstructure is studied in the frame of thin films deposited by inkjet-printing technology. The role of sintering temperature and thermal ramp is particularly investigated. Fast heating ramps exhibit coarse grains and pores, especially when a hybrid microwave curing is performed. This enhanced growth is attributed to the quick activation of densifying sintering regimes without undergoing thermal energy loss at low temperature. Microstructural evolution of various sintered inkjet-printed films is correlated with electrical resistivity and with the Young’s modulus determined by nanoindentation. A strong link between those three parameters is highlighted during experiments giving credit to either a surface or a fully volumetric sintering, according to the process. Sintering is then mainly triggered by surface mass transfer or by grain boundary diffusion. Silver thin films with an electrical resistivity 4–5 times higher than the bulk, has been reached in a few minutes with a Young’s modulus of 38 GPa.