The optical response of strained SiGe alloys, as well as thin Si layers, is analyzed using a sp(3)d(5)s* tight-binding model within the independent particle approximation. The theoretical results are compared to measurements obtained on samples with various Ge content and layer thicknesses. The dielectric function is extracted from spectroscopic ellipsometry allowing a separation of its real and imaginary parts. Theory and simulation show similar trends for the variation of the dielectric function of SiGe with varying Ge content. Variations are also well reproduced for thin Si layers with varying thickness and are attributed to quantum confinement. (C) 2016 Elsevier Ltd. All rights reserved.

The germanium fraction dependence of the Solid Phase Epitaxial Regrowth (SPER) rate in SiGe alloys has been investigated using a lattice kinetic Monte Carlo (LKMC) approach. Experiments show that the SPER rate is monotonically increasing with the addition of germanium. However, the extracted activation energy exhibits a non-linear evolution with the increase of germanium content. To investigate the influence of germanium in SiGe alloys, a comprehensive atomistic model is presented. The model focuses on the chemical bond types between the amorphous and the crystalline phases. As several recrystallization configurations exist at the amorphous–crystalline interface, a competition between them arises during SPER. This competition, implemented into a LKMC simulator, is able to reproduce several phenomena observed during SPER experiments on SiGe alloys: the monotonically increasing SPER rate and the non linear activation energy behavior regarding the germanium content as well as the temperature dependence on the extracted activation energy. The presented model is in close agreement with experimental data from literature.

The amorphization by implantation of strained silicon–germanium epitaxial layers is investigated by experiments and simulation according to the germanium content in the film and the implantation conditions. Experimental results are used to calibrate a numerical model based on a combined approach between a Binary Collision Approximation (BCA) module and a kinetic Monte Carlo (kMC) module. The calibration is implemented in the Synopsys Sentaurus Process simulator and a close agreement between simulations and experiments is shown. Experimental results show that by increasing the germanium concentration, amorphous thickness is reduced for high energy implantations. Germanium content seems to have less impact at low energy implantations.

The presence of capping materials during annealing (activation for example) can substantially impact the silicon junction profiles of Complementary Metal Oxide Semiconductor Field Effect Transistors (CMOSFET), depending on the nature of these layers. In this paper we specifically investigated the boron out-diffusion from a silicon junction into the silicon oxide in presence of a silicon oxide/silicon nitride capping bi-layer similar to the stacks used to form sidewall spacers. After 120 s anneal we observed with secondary ion mass spectrometry (SIMS) substantial boron dose loss in silicon and segregation at the silicon oxide interface related to oxide and nitride material properties, in particular to the hydrogen concentration. We then modeled the boron profiles in both silicon and oxide as a function of the hydrogen static and dynamic in the materials. The exponential-like boron diffusion profiles observed in oxide are reproduced by introducing a long hop mechanism mediated with hydrogen-related defects (HRDs). (C) 2016 Elsevier Ltd. All rights reserved.

In this paper a complete TCAD model addressing Hot Carrier Degradation for Flash technology is presented and its validity range extended respect to our previous work. Using the correlation of drifting electrical parameters, a simple technique for the analysis of trap distribution location is presented and physical insights on defect shape evolution are provided at different stress conditions.

We present an experimental technique and a Finite Element thermal simulation for the determination of the temperature elevation in Silicon on Insulator (SOI) MOSFETs due to self-heating. We evaluate the temperature elevation in two steps, as we calibrate the gate resistance over temperature with the transistor at off state at a first stage, and then we deduce the temperature elevation through gate resistance measurements. We simulate the self-heating phenomena in a Finite Elements Method (FEM) environment, both with 2D and 3D models. In order to set up the simulations, we weight the effects of several parameters, such as thermal material properties, the modeling of heat generation and a careful setting of boundary conditions. We present typical temperature fields and local heat fluxes, thus giving concrete indications for solving thermal reliability issues. Simulation results show temperature elevations up to approximately 120 K in the hot spot, 70 K in the gate and 7 K in the Back End of Line (BEoL). The 3D model gives results that are satisfying over the whole set of MOSFETs we consider in this work. Temperature elevation strongly depends on physical dimensions, where transistors endowed with shorter gates suffer from more severe self-heating. We propose a simplified model based on geometrical parameters that predict maximum and gate temperatures, obtaining satisfying results. Since correlation with measurements confirms the correctness of our model, we believe that our simulations could be a useful tool to determine accurate reliability rules and in a context of thermal aware design.

This paper aims at determining thermomechanical stress variations induced by annealed copper filled through-silicon via (TSV) in single crystalline silicon using metal-oxide-semiconductor (MOS) rosette sensors. These eight branches sensors were specifically designed and embedded in a 65-nm CMOS technology test vehicle. An in-house four-point bending tool was employed to calibrate and to extract the six independent piezoresistive coefficients. Through the piezoresistive relations, the stress tensor was evaluated by carrying out electrical measurements on wafer splits. A finite-element approach was also adopted to evaluate numerically the stresses and the expected mobility variations induced by TSV. According to this paper, a large variation of stresses (up to 100 MPa) in the sensor area was estimated, suggesting possible sensor design improvements to better accuracy. A good agreement was obtained between numerical and experimental results, except for the orthoradial component, which was found slightly compressive experimentally. Based on a critical analysis of the experimental-numerical methodology and results detailed in this paper, guidelines are drawn to get better accuracy through the improvement of MOS size and positions as well as recommendations regarding test strategy to overcome process variability. In the longer term, such improvements should lead to the definition of a comprehensive strategy for mechanical stress probing with in situ structures in advanced semiconductor products.

Lasers have become one of the most efficient means to attack secure integrated systems. Actual faults or errors induced in the system depend on many parameters, including the circuit technology and the laser characteristics. Understanding the physical effects is mandatory to correctly evaluate during the design flow the potential consequences of a laser-based attack and implement efficient counter-measures. This paper presents results obtained within the LIESSE project, aiming at defining a comprehensive approach for designers. Outcomes include the definition of fault/error models at several levels of abstraction, specific CAD tools using these models and new counter-measures well-suited to thwart laser-based attacks. Actual measures on components manufactured in the new 28 nm FDSOI technology are also presented.

This paper presents a modeling study of III-As materials' band structure obtained with a full-zone 54-band k· p model. This model, extending the 30-band model of Refs. [1], [2], accounts for (220) bands and allows a better description of the band structure in the vicinity of the K point [2]. The band gaps and effective masses derived from the band structure are compared with values obtained from other methods, such as the empirical pseudopotential method (EPM) and the tight-binding (TB) approach. Band structures for In x Ga 1−x As alloys with different In mole fraction x are computed within the virtual crystal approximation.

This paper provides a compact model for performance and process variability assessment in 14nm FDSOI CMOS technology. It is used to investigate MOS performance relation with process parameters. Then production device within wafer variability has been modeled using backward propagation of variance (BPV). This application allows spotting the main model parameter contributing to the total MOS transistor resistance (R on ) variability.

A complete TCAD model addressing Hot Carrier Degradation for Flash technology is presented. After having underlined the need for a power law with a low exponent for the aging kinetics and considered a high activation energy reflecting the single electron impact mode, a fine calibration is achieved. Finally, analysis on trap distribution and aging rates at different channel locations are provided

This paper reviews the main challenges for the TCAD of 14nm Fully-Depleted Silicon-On-Insulator (FDSOI) technology performance assessment. Thanks to a multi-scale approach combining extensive electrical characterization and advanced solvers simulations, ensuring deep physical insight, we provide TCAD simulation framework for device layout optimization, strain engineering and device reliability assessment.

In this work, innovative experiments and failure analysis during copper pillar shear test are described and complemented with simulation. The aims are to, firstly, establish several copper pillar bump failure scenarii and look into the alleged failure mechanisms involved during the shear test. It is accomplished experimentally by carrying out incremental tests on a 28nm CMOS technology test chip. More precisely, the shear tool is stopped at various stages during the test, and the subsequent FIB/SEM cross-sectional views are performed. Three main distinct modes are highlighted and discussed. The second aim of this paper is to investigate the design and layout effects (i.e. copper density in interconnect levels). To do so, different BEoL metallization densities are studied experimentally and numerically. During this dedicated campaign, the three aforementioned failure modes are also observed. Focusing on the cratering mode, which underlines a weakness at the BEoL level, experiments reveal that structures having the lowest metal density are more prone to fail than the balanced ones. Then, simulations are performed to give deeper understanding. Good agreement is found with the experimental observations, which highlights the impact of the BEoL structure on the reliability. Lastly, this work provides a comprehensive understanding of the BEoL behavior under bump shear loading, and enables further design optimization to secure assembly processes of advanced semiconductor technologies.

We have studied the mobility in the FDSOI devices as a function of silicon thickness, doping, surface orientation and applying different back biases. This study is also done in the near-spacer-region that is partially inverted. Simulations have been obtained with a self-consistent Poisson-Schrödinger which provides a precise energy distribution of carriers and, allied to a Kubo-Greenwood carrier mobility solver, performs a quantum corrected drift diffusion (QCDD) model, capable of capturing non local effects on transport (tunneling) and mobility (influence of geometry).

A complete TCAD model addressing Hot Carrier Degradation for Flash technology is presented. After having underlined the need for a power law with a low exponent for the aging kinetics and considered a high activation energy reflecting the single electron impact mode, a fine calibration is achieved. Finally, analysis on trap distribution and aging rates at different channel locations are provided.

This work aims at implementing sense structures dedicated to the determination of the electrical responses of device due to packaging and to find ways of minimizing the stress effects on typical devices. Calibration step is carried out thanks to a four-point bending machine on 4n&4p MOS rosette sensors and bandgap (BG) structure. It is combined to 3D finite element (FE) simulations with the Ansys software on two typical packages (a large and a small die). The results show significant mobility changes in distinct regions of the dies: up to -11% diminution was found on nMOS, while pMOS are boosted up to +4%. A dedicated simulation strategy is also proposed to make the bridge between the bandgap coefficients previously calibrated and the stress components. Package simulation results show variations of the output voltage around -0.35% at the central region of the large die and -0.24% for the small one. In addition, the larger the die is, the higher the variations are. In order to reduce the impact of packaging on the device shifts, parametric studies were performed on a standard package, consisting in the variation of several component features. This allowed obtaining the device shifts close to zero: nMOS→0.008%, pMOS→0.0012% and BG→10 -5 % over a large area in the middle of the die. These studies demonstrated that the effects of packaging steps at the transistor and circuit scales cannot be neglected anymore and that managing the components parameters can minimize these effects.

In the past few years, novel assembly schemes, such as Flip Chip, 3D assemblies, and advanced low-k/ultralow-k dielectric materials have been introduced in the semiconductor industry. Aiming to develop and grant maturity milestones, standardized procedures are used to assess the assembly reliability. Among them, bump shear test provides a quantitative measure of the bonding strength between the Bump, UBM and pad structure. In this paper, some investigations on the failure mechanism induced by shear test are proposed. At first, it is shown experimentally that, for similar structures, the failure mode depends on the shear tool standoff. More precisely, high height values promote the cratering mode (i.e. fracture in the interconnect layers) whereas low ones induce a ductile mode (i.e. fracture in the bulk Aluminum layer). A numerical model is carried out to provide a better understanding of the mechanisms. Finite element simulations highlight a strong variation of the peeling stress according to the shear height, whereas the shear stress component remains quite stable. Based on these experimental and numerical findings, distinct scenarii and criterion are proposed to explain the fails. This approach is consolidated by extending the comparisons with additional experimental results. At last, the preliminary results of a time dependent study (effect of the shear tool speed and a non linear copper law) are discussed. These first insights aim at giving additional input on the physics occurring during the test.The present work proposes a validated numerical basis to explain and forecast the failure mode preference during a bump shear test. This provides some clues for design guidelines, process integration and product developments. (C) 2015 Elsevier Ltd. All rights reserved.

During the assembly of Flip-Chip devices, some Chip-package compatibility concerns are observed while processing, such as reflow or thermal cycles. In this paper, some illustrations of failed copper pillar bump are presented and the associated failure modes are discussed. In this frame, dedicated numerical methodologies are proposed to take into account these interactions. The difference of scales between interconnects (~1μm), and package (~10 mm) components, the numerous bumps locations as well as the complex copper trace pattern of the substrate induce a large amount of elements and complex modeling. To manage these issues, several methods are used and described: Import of the copper trace pattern from CAD file, homogenization technique, multi-scale technique and dedicated scripts to automatically investigate local stress at all bump locations. Based on an actual product, typical results are depicted to illustrate the added-value of the developed methods. Focus is done on the package parameters such as bump design factors (pitch, rows number and layout) and substrate... Results show that by optimizing the densities and the bump locations with regard to the die, the stress induced by chip-package interactions can be significantly reduced. Pitch, presence of dummies bump or regular layout are underlined as key parameters. Moreover, a detailed analysis of the stress field nearby the bump according to its location with regard to the die is presented. By proposing simulation methodology including whole conception flow, this paper brings added values for product designers whose face mechanical Chip Package Interactions issues.