The execution of large-scale quantum algorithms remains constrained by the limited number of available qubits, restricted qubit connectivity, and the intrinsic noise in current quantum processors. To address these challenges, Dynamic Quantum Circuits (DQC) have emerged as a promising design paradigm that leverages non-unitary operations–such as active reset, mid-circuit measurement, and classically controlled gates–to reduce qubit requirements during circuit realization. While DQC offers significant resource savings, it often incurs a trade-off in the form of increased circuit depth, making the assessment of circuit reliability a critical concern for near-term quantum hardware. In this work, we analyze the structure of oracle functions and observe that transforming their global mappings into vector-valued forms provides key benefits, including reduced circuit depth, improved parallelism, and minimal additional gate overhead. These properties make the proposed approach particularly effective for architectures with limited qubit connectivity and distributed quantum systems with communication constraints. Furthermore, we introduce a DQC-based transformation scheme and demonstrate its application to the Bernstein-Vazirani (BV) and Quantum Phase Estimation (QPE) algorithms across varying circuit sizes. Empirical results confirm that the proposed design methodology improves execution efficiency and reliability as a function of qubit count and circuit depth, paving the way for scalable DQC-based implementations in resource-constrained quantum architectures.

Memristor crossbar is a suitable architecture to perform vector-matrix multiplication (VMM) and additionally offers benefits like in-memory computing (IMC), low power and high density. When a memristor crossbar is used for neuromorphic computing, the weights are stored in the form of resistance/conductance. However, the nonlinear switching behavior of memristors prevents their efficient use for neural network applications. The main challenge with nonlinear storage is the precise configuration of the memristor resistance/conductance values. Furthermore, due to the resistive storage technique, memristors do not allow negative network weight. A memristor-bridge-synapse ensures linear weight change and handles negative weights. However, it cannot be directly mapped to the crossbar. In this paper, we propose a crossbar architecture suitable for bridge-synaptic neurons. Implementing the bridge-synaptic network in the crossbar allows parallel weight updates and reduces overall training and inference latency. The effectiveness of the proposed bridge-crossbar mapping is validated through experiments on MNIST, Fashion-MNIST, and CIFAR-10 datasets, demonstrating improved accuracy over conventional single-crossbar implementations while maintaining robustness and scalability for both single-neuron and multi-neuron networks.

The execution of large-scale quantum algorithms is currently constrained by the limited number of available qubits, qubit connectivity restrictions, and the inherent noise in quantum processors. To address these limitations, a design methodology known as Dynamic Quantum Circuits (DQC) has emerged. DQC leverages non-unitary operations-such as active reset, midcircuit measurement, and classically controlled gate operationsto reduce qubit requirements during circuit design. Recently, DQC-based implementations have been explored for various algorithms, including Shor’s Prime Factorization, Quantum Phase Estimation (QPE), and Bernstein-Vazirani (BV), as well as for key operations like state preparation, Toffoli networks, and nonlocal gates. While DQC offers a significant reduction in qubit usage, it introduces a trade-off in the form of increased circuit depth. Therefore, assessing the reliability of such circuits becomes crucial in the context of current quantum hardware architectures. In this paper, we analyze the reliability of DQC-based quantum circuit realizations as a function of qubit count and circuit depth. We present empirical results for two algorithms and evaluate how architectural parameters impact their reliability.

The exponential growth of the Internet of Things (IoT) has led to a surge in data generation, critical for business decisions. Ensuring data authenticity and integrity over unsecured channels is vital, especially due to potential catastrophic consequences of tampered data. However, IoT’s resource constraints and heterogeneous ecosystem present unique security challenges. Traditional public key infrastructure offers strong security but is resource intensive, while existing cloud-based solutions lack comprehensive security and rise to latency and unwanted wastage of energy. In this paper, we propose a universal authentication scheme using edge computing, incorporating fully hashed Elliptic Curve Menezes–Qu–Vanstone (ECMQV) and PUF. This approach provides a scalable and reliable solution. It also provides security against active attacks, addressing man-in-the-middle and impersonation threats. Experimental validation on a Zybo board confirms its effectiveness, offering a robust security solution for the IoT landscape.

In this work mapping of quantum circuits to regular hexagonal grid with coupling degree of six has been investigated. Architectures involving superconducting qubits impose restrictions on 2-qubit gate operations to be carried out only between physically coupled qubits, also referred to as Nearest Neighbour (NN) Constraint. The noise introduced by the 2-qubit gates and the execution time greatly affect the computational reliability. Existing mapping techniques suffer either from the adopted approach to reduce gate overhead or from their inability to take advantage of such architectural regularity. We outlined three different qubit mapping approaches using Remote-CNOT templates, Swap gates and combination of both. We show the benefits of assigning the Cartesian coordinate system in hexagonal grid for runtime elevation and devised approaches for reduction in gate overheads. While the template-based approach gives a strict upper bound of additional gate overheads for a particular qubit mapping, the combined approach provides better result employing a larger lookahead window. Experiments on benchmark quantum circuits confirm that the proposed Swap-based method provides an average \(25\%\) improvement in gate overheads over a recent work and the combined approach contributes further \(15\%\) average improvement on the result at the expense of a little higher runtime.

The ability of resistive memory (ReRAM) to naturally conduct vector-matrix multiplication (VMM), the primary operation carried out in neural networks, has caught the interest of researchers. The memristor crossbar is a suitable architecture to perform VMM and additionally offers benefits like in-memory computation (IMC), low power, and high density. Memristor-based neural networks are typically trained using a mechanism where weight computations are carried out on a host machine and downloaded into the crossbar. However, due to faulty memristors in the crossbar, a cell may not be able to store the exact weight values, which may lead to inference errors. In this paper, we propose a weight-sharing method to improve the self-fault-tolerance capability of memristor crossbar. In order to reduce the impact of faulty memristors, the weights are shared among different layers of memristors in a 3D crossbar. Simulation analyses show considerable improvements in the fault-tolerance capability of the crossbar.

Quantum computing offers substantial speedup over conventional computing in solving certain computationally hard problems. The emergence of quantum computers in recent years has motivated researchers to develop design automation tools to map quantum circuits to such platforms. One major challenge is to limit the noise or computational error during gate operations; in particular, errors are higher when gates operate on non-neighbor qubits. A common approach to tackle this problem is to make the circuits Nearest-Neighbor (NN) compliant by inserting either Swap gates or CNOT templates . Reduction of gate overhead also becomes important as it serves to limit the overall noise and error. In some recent works, mapping of quantum circuits to hexagonal qubit architecture have been investigated. Hexagonal layout of qubits offers extended neighborhood that helps to reduce the number of Swap or additional CNOT gates required for NN-compliance. Existing approaches incur high gate overheads that can be reduced by improved gate mapping strategies with better cost metrics. The present work proposes one such approach using a priority-based cost metric. The proposed cost-metric is general and can be applied to any architectures; however, in this work we show its benefit for hexagonal architecture. Experiments on benchmark circuits confirm that the proposed method reduces gate overhead by 29 % over a very recent work based on greedy mapping.

Resistive random access memories (ReRAM) have drawn attention of researchers due to their unique properties with applications in in-memory computing, which allows storage and computation in the same unit. This mitigates one of the major limitations in current computing architectures, where for each computation we require to move data from memory to processor or vice versa, which incurs immense amount of energy overheads. Among the various technologies for implementing ReRAM, memristor is considered to be one of the most desirable candidates due to its small size, low power consumption, and high data retention. Such ReRAM systems are often fabricated in the form of crossbar for compact layout. However, they suffer from various challenges, one of the major ones being the sneak-path problem during reading of cell values. The read operation is mostly disturbed by sneak-path currents that can result in incorrect reading of the cell. This paper presents a new approach for reading the cell values in memristive crossbars, which is capable of avoiding erroneous read operations caused by sneak-paths. It also supports parallel operations whereby multiple memristor states can be read in a single cycle. A straightforward approach for reading all the cells in an n×n crossbar, where the read operation is performed sequentially, requires O(n2) cycles, whereas the proposed approach requires O(n) cycles.

Elementary gate decomposition of larger Toffoli operations is often carried out using additional qubits (ancilla). The number of gates and the circuit depth vary in such transformation depending on the type of ancilla used (clean or dirty). The present Noisy Intermediate Scale Quantum (NISQ) devices have limited number of coherent qubits with faulty native operation support. Superconducting devices also have coupling restrictions or Nearest-Neighbor (NN) constraints, which require additional gates to map the transformed netlist for execution. While the mapping overhead is correlated with the number of 2-qubit gates and involved qubits, the fidelity of execution is inversely proportional to the number of gates and circuit depth. There is a tradeoff in devising the transpilation (i.e. low-level transformation and mapping) approach — dirty ancilla demands less qubits and overhead at the expense of more gates and depth as compared to clean ancilla, which involves less gates and depth at the expense of more qubits and overhead. This paper analyzes the disparity in gates, depth and qubits between: (i) the low-level transformation approaches without considering device coupling information, and (ii) the mapping schemes based on netlist transformation using a specific type of ancilla. We analyze the benefits of using NN-constraints at the transformation stage, and the impact of distributing clean ancilla across architectures. We have carried out experiments on IBM Q20 and Hexagonal Q20 architectures, which show improvements of 17% and 13% respectively in terms of number of gates.

The ability of resistive memory (ReRAM) to naturally conduct vector–matrix multiplication (VMM), which is the primary operation carried out during the training and inference of neural networks, has caught the interest of researchers. The memristor crossbar is one of the desirable architectures to perform VMM because it offers various benefits over other memory technologies, including in-memory computing, low power, and high density. Direct downloading and chip-on-the-loop approaches are typically used to train ReRAM-based neural networks. In these methods, all weight computations are carried out by a host machine, and the computed weights are downloaded in the crossbar. It has been seen that the network does not deliver the same precision as promised by the host system once the weights have been downloaded. This is because crossbars contain a significant number of faulty memristors and suffer from cell resistance variations because of immature manufacturing technologies. As a result, a cell may not be able to take the exact weight values that the host system generates, and may lead to incorrect inferences. Existing techniques for fault-tolerant mapping either involve network retraining or employ a graph-matching strategy that comes with hardware, power, and latency overheads. In this paper, we propose a mapping method to tolerate the effect of defective memristors. In order to lessen the impact of faulty memristors, the mapping is done in a way that allows network weights to cover up faulty memristors. Further, this work prioritizes the different faults based on the frequency of occurrence. The mapping efficiency is found to increase significantly with low power, area and latency overheads in the proposed approach. Experimental analyses show considerable improvement as compared to state-of-the-art works.

The use of memristors has been explored for various applications due to its unique computing capability, in particular in-memory computing (IMC). IMC offers both storage and computation using the same hardware, which overcomes to a large extent the CPU-memory bottleneck that exists in current-day computing architectures. Memristors are often fabricated in a crossbar, which offers various benefits over other memory technologies, including in-memory computing, low power, and high density. However, the still immature nano-scale fabrication technology can lead to a number of faulty cells in the crossbar (typically, 30–40% faulty cells). For some applications like neuromorphic computing, a limited number of faults can be tolerated. However, for some other applications like Boolean function realization, a single faulty cell may lead to incorrect results. We therefore need a fault diagnosis approach to use the memristor devices efficiently. In this paper, we have analyzed various fault diagnosis approaches available in the literature. We observe that most of the existing approaches employ March-based test, which is used for conventional RAM. Nevertheless, memristor storage and operation techniques differ from conventional memory, necessitating a different approach and fault models to be used.

Motivated by physical realization of hexagonal architectures, in this paper we have introduced the hexagonal neighborhood structure for a set of qubits in a two-dimensional (2-D) plane along with a simple measure for estimating neighborhood distance. As compared to the traditional layout of qubits on a 2-D Cartesian plane, the hexagonal arrangement offers greater flexibility in mapping the logical qubits from a quantum circuit into an array of physical qubits. In most of the prior works, the neighborhood cost is estimated as number of Swap operations required to ensure that all 2-qubit quantum gates operate on physically adjacent qubits. However, in recent times, CNOT Templates have been used to execute 2-qubit gates where the interacting qubits are not adjacent to each other. In this paper we exploit the benefits of CNOT Templates in mapping quantum circuits to hexagonal 2-D arrays. We propose an evolutionary algorithm to obtain a good placement of qubits in the hexagonal structure. We also show the benefits of this approach over a simple greedy qubit placement method. We have carried out experiments on a set of benchmark suites to evaluate the efficiency of the proposed approach. The results show an average improvement of 42.9% over a very recent state-of-the-art method.

Memristors or Resistive Random Access Memory (RRAM) are emerging non-volatile memory devices that can be used for both storage and computing. In this type of memory the information is stored in memory cells in the form of resistance. One of the very important challenges in memristive crossbars is the existence of Sneak Paths, which result in erroneous reading of memory cells. Most of the logic in-memory techniques have emphasized on improving the logic design perspective, but have given minor importance to the sneak path issue. In this paper we show the effect of sneak paths on crossbars of various sizes, and then try to analyze the logic design approaches like MAGIC and MAJORITY with respect to their immunity to sneak paths. Experimental result shows that with some extra overhead we can eliminate the sneak path effect in various logic design methods.

This paper proposes a Finite State Machine (FSM) testing technique based on deep neural network (DNN). This technique verifies the correctness of an implementation FSM-B of a specification FSM-A. Using the back-propagation algorithm, a deep neural network is trained with the input–output patterns for a given set of transition functions that specify an FSM. Initially, for FSM-A, the input patterns and the corresponding output patterns (I/O pairs) are generated. Then most of the patterns are used to train the DNN. Once the training is over, the DNN is validated with the remaining I/O pairs (around 20%). The model can be used for verifying the correctness of FSM-B after training and validation of the DNN. Some inputs are applied to FSM-B and the generated output patterns are compared with the predicted values of the proposed DNN. The difference of accuracy percentages between FSM-A and FSM-B is recorded and zero difference between them indicates the fault-free condition of the implementation FSM-B. To check the effectiveness of the scheme, the output- and state-type faults are injected to derive mutant FSMs. Experimental results performed on the MCNC FSM benchmarks prove the efficacy of the proposed method. Only a few numbers of tests are needed to detect the presence of anomaly, if any. Hence, the test time reduces significantly — resulting in an average test time reduction of 85.67% compared to the conventional techniques. To the best of our knowledge, for the first time a DNN-driven testing scheme is being proposed.

Resistive memories have drawn the attention of researchers due to their low power and single-cycle computation of vector-matrix multiplication (VMM), which is the main operation performed in neural networks. For performing VMM, one of the most desirable architectures is the memristor crossbar that has several advantages over other memory technologies, viz. in-memory computation, low power, and high density. However, faults present in the crossbar can introduce errors in the inference process during neuromorphic computations. Existing methods to handle faults using retraining and remapping incur overheads in terms of hardware, power, and delay. In this paper we explore and analyze the impact of faults on memristor-based crossbar for overall inference accuracy. We have observed that the accuracy is not significantly affected in the presence of a limited number of faults. Also, the inference quality and effect of faults depend on the number of neural network layers and storage resolution of memristors present in the crossbar. The introduced approach works in three phases, fault tolerance analysis, high-level fault detection, and low-level fault detection. In the first phase, we analyze the fault tolerance capability of the crossbar, which identifies how many faults can be tolerated for a given application. In the second phase, we estimate the percentage of faults, and if it is below a threshold the third phase can be skipped. In the third phase, an efficient method to determine the exact location of the faults is used. The proposed method is capable of performing parallel operations, thus requiring fewer read/write steps as compared to existing works. The proposed approach requires O(N) read/write operations as compared to O(N-2) operations required in existing works.

The use of memristors, also known as Resistive Random Access Memory (ReRAM), has been widely investigated in recent years for non-volatile memory design applications. Memristors can also be used for realizing logic operations, leading to new in-memory computing (IMC) architectures. However, the presence of sneak paths in crossbar arrays limits the practical use of such systems. In this paper, we introduce a novel sneak path-free ReRAM system capable of both memory and logic operations using Complementary Resistive Switches (CRS) or Complementary Memristors (CMs) crossbar array. CMs can mitigate the effect of sneak paths and are good candidates for realizing three-dimensional memory array. A novel IMC-enabled two-dimensional (2D) and three-dimensional (3D) crossbar architecture have been proposed. The devices are modeled using the VTEAM memristor model and can perform majority (MAJ) gate operations directly on the crossbar. A logic mapping approach is also proposed, allowing serial and parallel evaluation of MAJ operations for given high-level logic functions. The efficacy of the approach has been evaluated by estimating the computation cycles, crossbar size, delay, and energy for various benchmark functions. The results show that the proposed method yields up to 91.19% improvement over an existing IMC method in computation steps and 78.90% reduction in terms of the number of memristors required.

We investigate the classical problem of conformance checking (CC) for non-scan synchronous sequential machines from a new perspective of "design-for-verifiability" utilizing a machine-learning framework. Given the specifications of a finite-state machine A and its circuit implementation B. the goal of CC is to verify the correctness of B. Conformance checking is a hard problem; typically, various formal methods, simulation techniques, and meta-heuristics are employed to resolve it. However, even for moderate-size FSMs, these approaches either become computationally unmanageable or are unable to provide adequate error coverage. In this work, we train a deep neural network (DNN) with a fraction of the I/O transitions of machine A. Following the training phase, the DNN is validated with the remaining I/O pairs. Next, given an input, its predicted output is compared with the one that is observed from its circuit implementation B, and prediction accuracy is recorded. In order to check the effectiveness of the scheme, various design errors, modeled by output- and transfer-type faults, have been injected in B to derive mutant circuits. Experiments show improvements with respect to CPU-time and error-coverage compared to earlier approaches reported in the literature. In the second part of the work, we adopt a technique for modifying circuit B by adding extra hardware so that the augmented machine becomes easily verifiable while preserving the original functionalities. The proposed modification, however, does not insert any scan-chain, and thus, it is not vulnerable to scan-based security threats. When DNN-aided experiments are performed on the modified machines, the parameters such as CPU-time or error coverage show improvements significantly. Experiments performed on MCNC and ISCAS-89 FSM-benchmarks demonstrate the efficacy of the proposed method.

Resistive memory systems, due to their inherent ability to perform Vector–Matrix Multiplication (VMM), have drawn the attention of researchers to realize machine learning applications with low overheads. In resistive memory systems, each memory cell (synapse/neuron) stores a weight in the form of resistance/conductance value. Memristor-based resistive memory has been widely explored in this regard because of its small size and low power consumption. The inference quality of a neural network depends on how efficiently and accurately the weights are stored in the synapses. The weights are calculated using various training algorithms, like back-propagation (BP), least mean square (LMS), and random weight change (RWC). The training accuracy of existing algorithms is directly related to the algorithm complexity and the time devoted for training. This paper presents a training algorithm that requires an additional set of memristors and a threshold gate for training and achieves an accuracy similar to existing algorithms without using any complex circuitry. The method can update synapse weights in parallel and requires fewer epochs for training an application. Results on experiments with standard benchmarks reveal that the method can achieve an average speedup of 38 × as compared to state-of-the-art methods. • Propose a training algorithm to improve the convergence speed. • Reduce the hardware complexity of the implementation. • Reduce the requirement of high precision memristors. • Update weights in parallel to reduce training time.