Memristor is considered as a promising circuit element which can be used in many applications. Various synthesis methods for Boolean functions have been explored in the literature using memristor-based design styles. Memristor crossbar is considered as one of the most preferred structures for implementing logic functions as well as memory. In this paper, a general synthesis flow has been proposed using the MAGIC logic design style to map multioutput Boolean functions to memristor crossbars. The functions are realized as a netlist of NOR and NOT gates. Two alternate methods of evaluating the gates are used, serial and parallel, which give a tradeoff between the number of cycles and the size of the crossbar. A strategy for scheduling the gates to time steps has also been proposed to reduce the hardware overhead. The switching delays and energy requirements are estimated using SPICE simulation. Synthesis results are reported for ISCAS'85 benchmark functions that show an average reduction of 68.8% in the number of cycles, 52.8% in energy consumption, and 96.4% in the number of memristors required as compared to a very recently published work.

Memristor is a two terminal passive circuit element that can be used in non-volatile storage applications. In addition, memristor can also be used to implement logic functions. This paper presents the design of adder circuits in memristor crossbar. We have used the MAGIC design style to implement the gates required for the adder circuits. The implementation is based on in-memory computing where the input data is assumed to be stored in the crossbar, and the processing is done in the storage unit itself. We have estimated the gate delay and switching energy using SPICE simulation under Cadence Virtuoso environment. We have evaluated the latency of the half adder, full adder, 4-bit ripple carry, 4-bit carry lookahead adder and generalized the latency and area estimates for an n-bit ripple-carry adder. The proposed method is compared with an alternate memristor based synthesis method (viz. IMPLY) and is found to be more efficient in terms of latency and energy with similar area overheads.

Because of their resistive switching properties and ease of controlling the resistive states, memristors have been proposed in nonvolatile storage as well as logic design applications. Memristors can be fabricated in a crossbar and suitable voltages applied to the row and column nanowires to control their states. This makes it possible to move toward new non-von Neumann-type architectures, usually referred to as in-memory computing, where logic operations can be performed directly on the storage fabric. In this paper, a scalable design flow for in-memory computing has been proposed, where a given multioutput logic function is synthesized as a netlist of NOT/NOR gates and then mapped to the crossbar using the Memristor-Aided loGIC (MAGIC) design style. The memristors corresponding to the primary inputs are initialized a priori. Subsequently, the required gate operations are performed by applying suitable row and column voltages in sequence. Two alternate mapping schemes have been analyzed. The switching characteristics of MAGIC NOR gates have been evaluated using circuit simulation under the Cadence Virtuoso environment. Experimental evaluation on ISCAS'85 benchmarks reports the average improvements of 27.7%, 34.6%, and 26.2%, respectively over a recently published work with respect to the number of memristors, number of cycles, and total energy dissipation, respectively. It may be noted that the energy consumption of the gates used in the proposed approach (NOT and NOR) is significantly higher than that using CMOS technology.

Memristor has drawn the attention of circuit designers for its non-volatility, and is considered as a viable candidate to replace CMOS technology in many applications. Another interesting characteristic of memristor is that it can be employed in crossbar array architecture that allows very high packing density. In addition to implementing high capacity storage systems, memristor can also be used to realize logic functions. In this paper, the Memristor Aided Logic (MAGIC) design style is used to map the NOR netlist of a given Boolean function to memristor crossbar arrays. Various optimization techniques have been used by scheduling the NOR gates to time steps in order to reduce the hardware cost. To illustrate the viability of the design methodology, full adder and ripple carry adder circuits have been studied and analyzed.