We measure times for complete solid phase crystallization (SPC) of hydrogenated amorphous silicon (a-Si:H) thin films that vary eight orders of magnitude, from a few ms to a few days. The time-to-crystallization activation energy is consistent with literature values of approximately 3.4 eV but the prefactor is markedly different for hot-wire chemical vapor deposition (HWCVD) films than for plasma-enhanced (PE) CVD films. The crystallized films were 0.3–2 μm thick, and deposited by high deposition rate (10-100 Å/s) HWCVD or standard PECVD onto glass substrates. We annealed these a-Si:H films over a wide temperature range (500 to 1100 °C) using techniques including simple hot-plates and tube furnaces, rapid thermal annealing by a tungsten-halogen lamp, and microwave electromagnetic heating at 2.45 GHz (magnetron) and 110 GHz (gyrotron).

In this paper we report on our work using in-situ real time spectroscopic ellipsometry (RTSE) to study the dynamics of hot-wire chemical vapor deposition (HWCVD) of hydrogenated amorphous silicon (a-Si:H) and epitaxial crystal silicon (epi-Si) for photovoltaic applications. We utilize RTSE as both an in-situ diagnostic and a post- growth analysis tool for a-Si:H/crystalline silicon heterojunction (SHJ) solar cells and epi-silicon films grown by HWCVD. RTSE enables precise thickness control of the 3 to 10 nm thick layers used in the SHJ devices, as well as monitoring crystallinity and surface roughness in real time. With the assistance of in-situ RTSE feedback we have achieved a photovoltaic energy conversion efficiency of 17% on an Al-backed p-type float-zone c-Si wafer. Open-circuit voltages above 650 mV indicate excellent passivation of the c-Si surface by the a-Si:H intrinsic layer. We have used RTSE to obtain information on the degree of crystallinity and the electronic and optical properties of films as a function of deposition conditions. RTSE has indirectly indicated the persistence of a hydrogen layer at the interface between the a-Si:H layer and the crystal silicon substrate. Absorption spectra determined by RTSE have provided guidance in device optimization. We are also applying in-situ RTSE to study the dynamics of HWCVD growth of epi- Si. The goal of this work is to develop low-temperature methods for growing 2–10 μm- thick layers of c-Si on c-Si seed layers on glass for solar cell applications. This study presents unique challenges for RTSE, as perfect epitaxial growth of c-Si on a c-Si wafer would produce no change at all in the RTSE spectra. We have found that by monitoring the pseudo-dielectric function in real time during growth we gain immediate feedback on the breakdown of epi-Si growth. Post-deposition analysis of the RTSE data provides quantitative information on the percent of c-Si and a-Si versus film thickness. The RTSE analysis has been confirmed by cross sectional TEM. Based on the rapid feedback provided by RTSE we have surpassed the previous HWCVD maxiumum of 200 nm of epi-Si growth, achieving a maximum thickness of 500 nm of epi-Si. TEM analysis has shown that micron-sized areas of these films achieve 1000 nm of epi-Si thickness.

We conduct a systematic investigation into the mechanism of hole collection in amorphous/crystalline silicon heterojunctions solar cells using transient-capacitance techniques. The devices are formed by depositing undoped amorphous silicon (i layer) followed by p-type amorphous silicon on n-type crystalline silicon wafers. For i layers varying from 3.2 to 96 nm, we find only a factor of four change in hole collection-rate at low temperature where thermal emission over the valence band offset is precluded. We conclude that holes traverse the i layer by hopping through defects rather than direct tunneling through the entire i layer. This process is weakly thermally activated with a rate above 1 × 104 s−1 at room temperature. Near room temperature and with thick i layers, we observe hole collection with a high activation energy that depends on measurement conditions. We demonstrate that hopping through defects is the dominant mode of hole collection for solar cell operation at room temperature and above.

Crystal silicon (c-Si) film photovoltaics (PV) fabricated on inexpensive substrates could retain the desirable qualities of silicon wafer PV—including high efficiency and abundant environmentally-benign raw materials—at a fraction of the cost. We report two related advances toward film c-Si PV on inexpensive metal foils. First, we grow heteroepitaxial silicon solar cells on 2 kinds of single-crystal Al2O3 layers from silane gas, using the rapid and scalable hot-wire chemical vapor deposition technique. Second, we fabricate heteroepitaxial c-Si layers on large-grained, cube-textured NiW metal foils coated with Al2O3. In both experiments, the deposition temperature is held below 840 °C, compatible with low fabrication costs. The film c-Si solar cells are fabricated on both single-crystal sapphire wafer substrates and single-crystal γ-Al2O3-buffered SrTiO3 wafer substrates. We achieve ∼400 mV of open-circuit voltage despite crystallographic defects caused by lattice mismatch between the silicon and underlying substrate. With improved epitaxy and defect passivation, it is likely that the voltages can be improved further. On the inexpensive NiW metal foils, we grow MgO and γ-Al2O3 buffer layers before depositing silicon. Transmission electron microscopy (TEM) and X-ray diffraction (XRD) confirm that the silicon layers are epitaxial and retain the ∼50 μm grain size and biaxial orientation of the foil substrate. With the addition of light-trapping, >15% film c-Si PV on metal foils is achievable.

We have achieved the best open-circuit voltage (Voc = 0.94 V) to-date in hydrogenated amorphous silicon (a-Si:H) photovoltaic cells deposited entirely by hot-wire chemical vapor deposition. The fill factor (FF = 0.74) remained high and a current density of 8–9 mA/cm2 with about 1800 Å i-layer was obtained in our n-i-p cells on untextured stainless-steel substrates. The Voc improvement of about 60 mV in compared to our previous best Voc was obtained by incorporating materials grown with H-dilution close to the phase transition from amorphous to microcrystalline silicon in the i-layer and at the i-p interface. A low substrate temperature of 150°C for the i-layer was also essential, most likely to widen the bandgap of the i-layer. A brief atomic H-treatment after grown the i-layer increases the Voc further by improving the p-i interface. The last 60 Å of the i-layer before p-layer is extremely close to the transition to microcrystallinity, though it remains mainly amorphous. Our p-layers are also close to the phase transition.

Crystal silicon is an excellent photovoltaic (PV) semiconductor: silicon is abundant, environmentally benign, capable of high solar conversion efficiencies, and profits from an unparalleled scientific knowledge base. However, the energy-intensive, inefficient and expensive processes that turn sand into a crystal silicon (c-Si) wafer account for more than half of today s Si PV module costs. Because the peak flux of solar energy on Earth is only about 1 kW/m2, large areas must be covered with inexpensive PV to provide for TW-scale electrical power needs. To circumvent the costly wafer fabrication step, it would be ideal to grow 2-20 micron thick PV-quality silicon absorber layers directly from silane gas onto inexpensive substrates at temperatures below 800 C.

Light trapping plays an important role to achieve high short circuit current density (Jsc) and high efficiency for amorphous/crystalline Si heterojunction solar cells. Si heterojunction uses hydrogenated amorphous Si for emitter and back contact. This structure of solar cell posses highest open circuit voltage of 0.747 V at one sun for c-Si based solar cells. It also suggests that over 25% record-high efficiency is possible with further improvement of Jsc. Light trapping has two important tasks. The first one is to reduce the surface reflectance of light to zero for the solar spectrum that Si has a response. The second one is to increase the effective absorption length to capture all the photon. For Si heterojunction solar cell, surface texturing, anti-reflectance indium tin oxides (ITO) layer at the front and back are the key area to improve the light trapping.

We have explored which deposition parameters in Hot Wire CVD have the largest impact on the quality of microcrystalline silicon (μc-Si) made at deposition rates (Rd) > 10 Å/s for use in thin film solar cells. Among all parameters, the filament temperature (Tfil) appears to be crucial for making device quality films. Using two filaments and a filament-substrate spacing of 3.2 cm, μc-Si films, using seed layers, can be deposited at high Tfil (∼2000°C) with a crystalline volume fraction > 70–80 % at Rd’s > 30 Å/s. Although the photoresponse of these layers is high (> 100), they appear not to be suitable for incorporation into solar cells, due to their porous nature. n-i-p cells fabricated on stainless steel with these i-layers suffer from large resistive effects or barriers, most likely due to the oxidation of interconnected pores in the silicon layer. The porosity is evident from FTIR measurements showing a large oxygen concentration at ∼1050 cm-1, and is correlated with the 2100 cm-1 signature of most of the Si-H stretching bonds. Using a Tfil of 1750°C, however, the films are more compact, as seen from the absence of the 2100 cm-1 SiH mode and the disappearance of the FTIR Si-O signal, while the high crystalline volume fraction (> 70–80 %) is maintained. Using this Tfil and a substrate temperature of 400°C, we obtain an efficiency of 4.9 % for cells with a Ag/ZnO back reflector, with an i-layer thickness of only ∼0.7 μm. High values for the quantum efficiency extend to very long wavelengths, with values of 33 % at 800 nm and 15 % at 900 nm, which are unequalled by a-SiGe:H alloys. Further, by varying the substrate temperature to enable deposition near the microcrystalline to amorphous transition (‘edge’) and incorporating variations in H2 dilution during deposition of the bulk, efficiencies of 6.0 % have been obtained. The Rd’s of these i-layers are 8–10 Å/s, and are the highest to date obtained with HWCVD for microcrystalline layers used in cells with efficiencies of ∼6 %.

Solid state crystallization of hydrogenated amorphous silicon (a-Si:H) prepared by hot-wire CVD is studied in solid phase epitaxy mode. By using a novel optical method combined with cross-sectional TEM and SIMS, a reduction of epitaxial growth speed is observed with increase in a-Si:H film thickness. Namely, in films thinner that 0.9 micron, solid phase epitaxy velocity depends linearly on film thickness. As the film thickness increases beyond 1 micron, the average velocity of solid phase epitaxy decreases considerably with respect to that in thinner films. In this regime, its velocity becomes also time-dependent: initial slow propagation of crystallization front gets considerably accelerated after the front has traveled above 400nm. SIMS depth profiles of hydrogen shows considerably more residual hydrogen in thicker films after the start of solid phase epitaxy. In addition, prolonged pre-dehydrogenation at lower temperatures results in the increase in the average epitaxy speed in thicker films. These phenomena are likely related to delayed hydrogen outdiffusion in thicker films, which also leads to time-dependent speed of the solid-phase epitaxy front. Thus, the excess residual hydrogen in CVD films reduces the rate of solid-phase crystalline growth, similarly to earlier results on H-implantation and indiffusion.

We study the effect on various properties of varying the intrinsic layer (i-layer) thickness of amorphous/crystalline silicon heterojunction (SHJ) solar cells. Double-side monocrystalline silicon (c-Si) heterojunction solar cells are made using hot-wire chemical vapor deposition on high-lifetime n-type Czochralski wafers. We fabricate a series of SHJ solar cells with the amorphous silicon (a-Si:H) i-layer thickness at the front emitter varying from 3.2nm (0.8xi) to ~96nm (24xi). Our optimized i-layer thickness is about 4nm (1xi). Our reference cell (1xi) performance has an efficiency of 17.1% with open-circuit voltage (Voc) of 684mV, fill factor (FF) of 76%, and short-circuit current density (Jsc) of 33.1mA/cm2. With an increase of i-layer thickness, Voc changes little, whereas the FF falls significantly after 12nm (3xi) of i-layer. Transient capacitance measurements are used to probe the effect of the potential barrier at the n-type c-Si/a-Si interface on minority-carrier collection. We show that hole transport through the i-layer is field-driven transport rather than tunneling.

μc-Si has traditionally been deposited by Hot Wire CVD at a low filament temperature. At these temperatures, silicides rapidly form on the filament surface, leading in the case of a tungsten filament to both film reproducibility and filament lifetime issues. By depositing films consecutively using identical deposition parameters, these issues are chronicled for a filament temperature of ∼ 1750°C. Upon increasing the filament temperature to ∼ 1825-1850°C, these reproducibility and lifetime issues disappear and, by lowering both the substrate temperature and chamber pressure, device quality μc-Si is deposited at high deposition rates in a filament regime where tungsten silicide formation is minimal. Both single junction and tandem solar cells are fabricated using this material, confirming the validity of this approach.

We use capacitance techniques to directly measure the Fermi level at the crystalline/amorphous interface in n-type silicon heterojunction solar cells. The hole density calculated from the Fermi level position and the inferred band-bending picture show strong inversion of (n)crystalline silicon at the interface at equilibrium. Bias dependent experiments show that the Fermi level is not pinned at the interface. Instead, it moves farther from and closer to the crystalline silicon valence band under a reverse and forward bias, respectively. Under a forward bias or illumination, the Fermi level at the interface moves closer to the crystalline silicon valence band thus increases the excess hole density and band bending at the interface. This band bending further removes majority electrons away from the interface leading to lower interface recombination and higher open-circuit voltage.

We report on the first known growth of high-quality epitaxial Si via the hot wire chemical vapor deposition (HWCVD) method. This method yields epitaxial Si at the comparatively low temperatures of 195° to 450°C, and relatively high growth rates of 3 to 20 Å/sec. Layers up to 4500-Å thick have been grown. These epitaxial layers have been characterized by transmission electron microscopy (TEM), indicating large regions of nearly perfect atomic registration. Electron channeling patterns (ECPs) generated on a scanning electron microscope (SEM) have been used to characterize, as well as optimize the growth process. Electron beam induced current (EBIC) characterization has also been performed, indicating defect densities as low as 8×104/cm2. Secondary ion beam mass spectrometry (SIMS) data shows that these layers have reasonable impurity levels within the constraints of our current deposition system. Both n and p-type layers were grown, and p/n diodes have been fabricated.

Efficient crystalline silicon heterojunction solar cells are fabricated on p-type wafers using amorphous silicon emitter and back contact layers. The independently confirmed AM1.5 conversion efficiencies are 19.3% on a float-zone wafer and 18.8% on a Czochralski wafer; conversion efficiencies show no significant light-induced degradation. The best open-circuit voltage is above 700 mV. Surface cleaning and passivation play important roles in heterojunction solar cell performance.

We study amorphous/crystalline silicon heterojunctions (Si HJ) in both p-type and n-type c-Si solar cells under high level of photon injection using concentrated light up to 55 suns. The performance of the cells under intensive light is similar to other types of crystalline Si solar cells. The open circuit voltage (Voc) increases logarithmically with light intensity for both n-type and p-type base cells and best 760 mV at 48 suns. The best cell efficiency peaks around 10 suns at 19.6% on an untextured p-type Si HJ cell. It represents an 11% increase of the efficiency relative to the one at 1 sun. The decrease of cell efficiency at a higher light intensity is mainly due to the decrease of fill factor (FF). We also found that the FF decreases much quickly in the cell with an n-type wafer compared to a p-type wafer. After more experiments with controlled front finger space, wafer bulk resistivity, and the area of the cells, we conclude that there is a difference in carrier collection for the heterojunction emitters of the n-type and of the p-type c-Si solar cells under intensive illumination.

Optical second harmonic generation (SHG) has a long history of being used to selectively characterize surfaces and interface in a variety of materials, including semiconductors. Here, we briefly summarize the physics of SHG and explain why it is a promising characterization technique for photovoltaics (PV), where interfaces and surfaces play critical roles in device performance. We then show experimental results of initial SHG measurements performed on silicon heterojunction solar cells as they are swept through current-voltage curves.

We describe recent progress in developing epitaxial film crystal silicon (c-Si) solar cells that can be grown at low temperature (< 760 degrees C) on seed-on-glass substrates. This low-cost approach is enabled by rapid epitaxy (up to 300 nm/min) of Si films with low dislocation density (< 1x10(5) cm(-2)) at glass-compatible temperatures by hot-wire chemical vapor deposition (HWCVD). Epitaxial test cells on heavily-doped 'dead' Si wafers provide insight into the quality of the Si absorber and the physics that limit device performance. Our best 2-3 mu m thick, film silicon heterojunction (c-Si/a-Si) solar cells have reached similar to 6.7% efficiency (Voc similar to 570 mV, Jsc similar to 18 mA/cm(-2)) without rapid thermal anneal, defect passivation or light trapping. Unpassivated dislocations are strong recombination centers and limit effective minority carrier diffusion lengths to less than 15-20 mu m (roughly half the distance between dislocations). We also report devices without light-trapping on layer-transfer Si seed layers bonded to display-glass; these seed layers template growth of high-quality HWCVD cSi. Our initial devices have Voc = 460 mV, Jsc = 16.2 mA/cm(2), Eff. = 4.8 %, but will benefit from post-growth anneals, hydrogenation and new surface treatments before epitaxy. We discuss junction transport physics in the devices and explore the role of post-growth H-passivation and rapid thermal annealing treatments on device performance.

High efficiency crystalline Si heterojunction solar cells have been achieved with an independently-confirmed efficiency of 19.3% on a p-type silicon wafer. The hydrogenated amorphous silicon (a-Si:H) emitter and back contact were deposited using high-rate hot-wire chemical vapor deposition. This high efficiency cell has an open circuit voltage of 0.678 V, fill factor of 78.6%, and short circuit current density of 36.2 mA/cm2. Improved surface texturing, surface cleaning, back contacts, indium tin oxide (ITO) thickness, and surface passivation all contribute to the high efficiency. The high open circuit voltage results from the good amorphous Si surface passivation with a minority carrier lifetime of ~ 1 ms. Light management was applied to further improve the cell performance. ITO layer was optimized to maximize the current collection. This layer acts as a transparent contact layer to the emitter as well as a single anti-reflectance layer to minimize the optical loss due to reflection.