In this work, we explored an efficient automatic layout routing algorithm for connecting the power and ground pins in analog integrated circuits. A rectilinear minimal spanning tree (RMST) algorithm for two sets of pins is developed, in which minimal spanning tree is used to form the initial connections between pins. The obstacle-avoiding maze routing algorithm is used to break and reconnect the power and ground nets to avoid any short circuit. The genetic algorithm (GA) is further introduced to optimize the total connection wirelength. We also expanding the wire width to avoid electromigration and IR-drop.
The periodic stacked film etching is a key enabler of 3D device manufacturing. This work demonstrates a silicon oxide/tungsten/titanium nitride periodic stack etching in one etching step. Because of the chemical reaction mechanism differences for various materials, a wave-like sidewall is always observed after one step etching. Sub-100nm holes on single and periodic stacks are etched with Cl2/NF3/C4F6/Ar gases. By tailoring the gas ratio and bias power, passivation distribution and ion bombardment strength are optimized and a smooth sidewall with an excellent vertical profile is achieved.
Previously in 2020, the author proposed a new unified theory regarding the image force dielectric constant for Schottky emission leakage current in high-k dielectric. In this paper, the author will try to point out that this theory can be applied to ferroelectric hafnium zirconium oxide (HfZrO) capacitor structures.
As for engineering verification, such as three-temperature test, corner test and wafer factory transfer, some experimental processing has been done on the chip, resulting in some parameters of the chip being slightly shifted compared with normal bin1 chip. As a result, some marginal fail would occur if tested by normal FT (Final Test) program. But these chips are good at EVB (Evaluation Board) verification. In this case, if need a test program to cover these chips, test engineers need to increase power voltage or slow frequency for the corresponding test item. In SMT7 (Smartest7) program, it may need to modify hundreds of level or timing spec (specification) values and generate a test program with a new, loosen spec value, which would take at least one day. This paper introduces a solution that can provide a simple excel format tool for input modification, a flexible operator configuration to deal with spec value and develop a new test program with the click of a few buttons. It’s highly integrated, comprehensively improves program development efficiency and is easy to use.
Spiking Neural Network (SNN) mimics the biologically inspired neural network that benefits for the computing with low power and high parallelism. In this paper, a scalable and configurable low-power mixed signal neuromorphic accelerator is proposed for the SNN application. It consists of 64 neurons, 64 synapses, 64×64 Static Random-Access Memory (SRAM) array, 64×64 Content Addressable Memory (CAM) array and a number of digital asynchronous routers. 15×64 neurons are fully connected by proposed scalable architecture. The proposed neuromorphic accelerator is designed in 65 nm CMOS process dissipating 4.8 mW at 100 MHz of clock frequency from a 1.2 V power supply.
An improved delay-based noise canceling (DNC) sturdy 2-1 MASH Sigma-Delta modulator is designed in this paper, which eliminates the quantization noise of the first noise shaping loop compared with the traditional structure. SAR quantizer and data weighted average (DWA) are used to reduce the nonlinear problem of power consumption and feedback DAC. The circuit design uses $0.18\mu \mathrm{m}$ CMOS standard technology, the working power supply voltage is 3.3V, the sampling rate is 2.56MHz, the signal bandwidth is 20kHz, the peak SNDR is 102.2dB, the significant bit is 16.68bit and the overall power consumption is 2.87mW.
Program/Erase Cycling is the most important reliability index for NAND flash devices. There are many factors that can affect the cycling performance. Two major leakage models: floating gate to channel and bit line interference are investigated in this paper. Correspondingly, two process optimization schemes are proposed, including carbon-doped polysilicon floating gate and Active Area rounding corner. Cycling performance improvement has been demonstrated by ECC correction ratio reduction and break down voltage test after cycling.
The silicon pixel sensor (SPS) for X-ray free electron laser detection requires ultra-high operating voltage. In this paper, for an optimized multi-guard rings, a SPS with ultra-high breakdown voltage and low leakage is obtained. The effect of the arrangement of the multi-guard rings on the SPS breakdown is investigated by TCAD simulation. It is found that SPS with a gradually increasing gap from inner ring to outer ring has a higher breakdown voltage. Guided by this, the multi-guard ring structure of SPS is optimized and applied into the manufacture of devices. Finally, the optimized SPS exhibits an ultra-high breakdown voltage of exceeding 1,800 V; and the dark current of per pixel is approximately 2.0 pA at a bias voltage of 1,000 V.
In the metal layer of the integrated circuit, the layout has dense lines with high density and isolated lines with low density. The T-opening is in an isolated position in the layout. However, dense lines have mismatched process windows with isolated lines in the metal layer, lowering the process window with T-openings and analogous structures. Sub-Resolution Assist Feature (SRAF) is often used to improve the contrast, depth of field, and process redundancy of the lithography process to improve the process window of the layout in integrated circuits. Due to the different density features between the upper and lower (longitudinal) distribution of the horizontal pattern in the T-shaped opening, the diffraction spectrum distributions around the horizontal main pattern generate high discrepancy. As a result, the diffraction spectrum difference will lead to the mismatch of the process windows and reduce the process window of the layout. Here, we introduce a multi-step SRAF addition method evenly to reduce the contrast of graphics with different sizes, then improve the difficulty of the photolithography process.
Tri-layer mask scheme including photoresist (PR), Si-based anti-reflection coating (SiARC) and spin-on carbon (SOC) is applied to transfer PR pattern and shrink the critical dimension (CD) to the underneath patterning layer (PL). However, due to the presence of different pitches, SiARC residues were often observed on the remained pattering layer after the etch and the wet clean, especially on the patterns with the larger pitches. However, the trade-offs between the SiARC residue removal efficiency and the profile control bring big challenges for finding proper solution that only fully removes the residues but minimizes profile change. In this study, the reason for the formation of SiARC residues is illustrated. Moreover, we show how to balance these trade-offs to eliminate the SiARC residues but also to minimize the profile changes.
With 2D NAND flash technology reached 24nm and beyond, tiny defects including bridge and pattern collapse have become the major yield killer defect in AA loop. In this work, the mechanism of tiny bridge and pattern collapse defect formation and improvement solutions are studied. For tiny bridge defect, the results showed that PR residue by periphery AA photo insufficient development in self-aligned double patterning process is the major cause of tiny bridge defect. Enhanced photo rinse & puddle process, SADP core/spacer line CD inline control and core etch profile optimization are all effective solutions to reduce tiny bridge defect. For pattern collapse defect, repeating structures with high aspect ratio are vulnerable by surface tension of drying liquid between patterns. Optimized wet cleaning sequence to ensure structure in continuous wetting status showed great improvement for pattern collapse defect reduction.
Copper damascene metallization has been widely utilized in integrated circuit fabrication to form metal interconnect structures through electrochemical plating (ECP) technology. When some large pads are patterned on incoming wafers, excessive dishing profiles are often observed after ECP and chemical mechanical polishing (CMP) process. Solutions to overcome overpolishing issues involve optimization of both CMP and ECP processes. For ECP process, leveler additives in plating solution are the major contributor to leveling the big pad. By adjusting the rotation speed of the wafer during plating steps, the mass transfer of large organic molecules near the wafer surface can be varied. In this work, it is observed that the total dishing defect count under optical microscope observation can be significantly reduced by decreasing the rotation speed during plating. It is expected that this study will be beneficial to copper electrochemical deposition for wafers with large Cu pads.
This paper reported a novel alignment optimization method to improve on-product overlay (OPO) on an immersion lithography layer. Results show that the optimized alignment strategy makes the decorrected overlay improve 18.6% and 43.9% in the x/y directions, respectively. Budget breakdown shows the main residual overlay performance indicator (ROPI) variations from the common wafer $2 ^{nd}$ and $3 ^{rd}$ terms. Compared with the default alignment strategy, the optimized alignment strategy with high order wafer alignment (HOWA3) control solution brings much benefit in reducing lot-to-lot variation, which can increase OPO by $\sim 36.4$%/7.6% in x/y directions. The alignment optimization method is an effective method to improve OPO.
Effects of 14.9 MeV neutron irradiation on the carrier concentration ($N_{S}$) and deep-level traps were analyzed for n-GaN Schottky barrier diodes (SBDs). Neutron irradiation caused a minor positive shift of threshold voltage and typically unchanged reverse leakage current. As the irradiation fluence was increased up to $8\times 10^{14}{\mathrm n/cm}^{2}$, the net carrier concentration was significantly decreased, showing carrier removal effect. Concentration of two shallow traps (E1 and E2) in the GaN epi-layer was enhanced upon neutron irradiation, as revealed by deep-level transient spectroscopy (DLTS). A new deep-level trap E4 ($\mathrm{E}_{\mathrm{C}}$-0.64eV) was spotted for neutron-irradiated samples. Analysis of DLTS amplitude suggested that E4 was associated with extended defects rather than point defects. The results indicate that the GaN SBDs are promising for operations in high-dose neutron radiation environments.
In previous work we have shown a few typical patterns containing 45-degree local interconnection in the BEOL layers under 7 nm logic design rules. Our simulation result has demonstrated that the 45-degree design can save mask area up to 20%. As illumination source optimization has been widely applied in lithography in advanced technology nodes for improving process window, in this work, we will report a study on the subject that, with source optimization, how the SO may affect the process window in the patterns containing the 45-degree design. Some typical patterns using conventional design rules will be presented first, then the 45-degree interconnection design will be fully investigated under illumination source optimization.
Piezoelectric aluminum nitride (AlN) and scandium nitride (AlScN) thin films using reactive pulsed DC magnetron sputtering have shown the grown films on silicon (100) substrates without arcing during the deposition. Limited in-depth DC pulse studies have been done on the role played by variables like pulse frequency, duty cycle, and reverse voltage in the deposition process, despite the fact that many researchers have now demonstrated that pulsed DC magnetron sputtering can be used frequently to produce fully dense, defect-free films. Operating conditions were routinely altered, and the deposition technique was continuously updated. The goal of this study is to look at how the pulse parameters affected the deposition process and then how the pulse parameters and the film properties are correlated. Fifteen (15) distinct design of experiment (DOE) combinations by Box-Behnken experimental method on pulse parameters were executed for film deposition and characterized the films crystallinity, microstructures, and surface roughness to find out film properties in correlation with pulse parameters. This is the way that used for obtaining optimal pulse conditions is based on the subsequent response surface method (RSM) of DOE model.
Silicon nitride (SiN) hard mask (HM) has been investigated to achieve sub-100nm of high aspect ratio (HAR) pattern. In this study, SiN HM trimming technique is developed by mean of cyclic reactive ion etching (RIE) for the vertical profile required in advanced DRAM memory fabrication. Furthermore, the SiN CD trim rate is revealed as ~ 2 nm per cycle.
Electrostatic Discharge (ESD) compliant interconnects are critical to protect internal circuitry. Full chip dynamic simulation can’t be a practical solution now, the compliance is analyzed in static points-to-points effective resistance (P2PR) and current density of interconnects along as-designed ESD paths. This paper focuses on P2PR. Performing ESD paths P2PR measurements on full chip are performance challenging, analyzing ESD paths P2PR incompliance are very complex too. This paper introduces two essential steps to make ESD paths P2PR measurement & incompliance analysis feasible on full chip production design flow. They are Power& Ground routing networks pruning in graph theory assisted by manufacturing data, and a reliable method to breakdown lumped P2PR value into resistance contribution by layer for incompliance analysis to help layout fix.
Delamination or cracks within miniaturized semiconductor devices may occur due to the weaker adhesion of the Ag-Epoxy molding compound (EMC) interface compared to the Cn-EMC interface. To enhance the reliability of Integrated Circuit (IC) packages, adhesion promotion via surface organic/inorganic modifications to the silver surface have been the subject of many studies. An alternate approach is to improve the mold adhesion by roughening the silver surface. This paper described a new electrolytic rough silver-plating process. Roughened silver deposits, controlled by adjusting plating parameters, were obtained directly without loose particles. The resultant roughness demonstrated a positive correlation to the adhesion force of Ag-EMC.
Transmitting signals from one port to different ports at low temperature is necessary in superconducting quantum test system. An on-chip superconducting quantum transponder (SQT) is designed. The SQT has the function of routing signals from one port to multiple ports. Routing signals from one port to different ports can be realized through the impedance match between SQUIDs and output ports. In addition, due to the non-reciprocity of SQT, the isolation between sources and receivers can be achieved. The dual function of “transmit” and “isolate” may play an important role in superconducting quantum computing.
