We discuss the key features of a 300mm integrated Silicon MOS platform to serve as a basis for spin-qubit device exploration. The process yields structures with a pitch of 100nm and below, without bearing the complexity of advanced optical lithography, and retains high flexibility for fast device design adjustment.

In this paper, we combine multiphysics simulation methods to assemble a comprehensive design methodology for silicon qubit devices. Key device parameters are summarized by modeling device electrostatics, stress, micro-magnetics, band- structure and spin dynamics. Based on the models, we infer that highly confined single electron qubits in quantum dots, with large orbital energy separations, can be induced in Si-MOS structures with thin (t OX <; 20 nm) gate oxides. We further advocate that poly-silicon gate material, in conjunction with small barrier gate widths (b <; 30 nm), will reduce the impact of strain on qubit readout and two-qubit gate-operations. We optimized a micromagnet design to provide fast single-qubit gate times (~100 ns), with minimal dephasing field gradients. Finally, we estimate that the exchange coupling between qubits is tunable by over 4 orders of magnitude, for two-qubit operations.

In this letter, we show that conventional III-V MOSFETs with moderate/high In content channels (In0.53Ga0.47As or In0.70Ga0.30As) at scaled nodes are incompatible with mobile SoC designs, which often operate at intermediate/high V-dd (0.7 V to >= 1 V) to achieve high frequency including during burst-mode. The incompatibility is due to conventional III-V FETs having too small bandgap, and thus too high leakage when operated at the increased voltages. We show that FETs with a more optimal lower In content, In0.35Ga0.65As, have the necessary combination of larger bandgap (similar to Si) and sufficiently high injection velocity (similar to 2.5 times Si) to enable both low leakage and high performance (versus Si), across the entire Vdd range of mobile SoC operation. We report for the first time the growth and characterization of ultra-thin In0.35Ga0.65As FETs with a standard 1nm EOT gate dielectric. Calibrated models show that In0.35Ga0.65As enables the highest performance at very low leakages at intermediate/high Vdd in short channel FETs.