In this letter, we show that conventional III-V MOSFETs with moderate/high In content channels (In0.53Ga0.47As or In0.70Ga0.30As) at scaled nodes are incompatible with mobile SoC designs, which often operate at intermediate/high V-dd (0.7 V to >= 1 V) to achieve high frequency including during burst-mode. The incompatibility is due to conventional III-V FETs having too small bandgap, and thus too high leakage when operated at the increased voltages. We show that FETs with a more optimal lower In content, In0.35Ga0.65As, have the necessary combination of larger bandgap (similar to Si) and sufficiently high injection velocity (similar to 2.5 times Si) to enable both low leakage and high performance (versus Si), across the entire Vdd range of mobile SoC operation. We report for the first time the growth and characterization of ultra-thin In0.35Ga0.65As FETs with a standard 1nm EOT gate dielectric. Calibrated models show that In0.35Ga0.65As enables the highest performance at very low leakages at intermediate/high Vdd in short channel FETs.

InGaAs-based Gate-all-Around (GAA) FETs with moderate to high In content are shown experimentally and theoretically to be unsuitable for low-leakage advanced CMOS nodes. The primary cause for this is the large leakage penalty induced by the Parasitic Bipolar Effect (PBE), which is seen to be particularly difficult to remedy in GAA architectures. Experimental evidence of PBE in In70Ga30As GAA FETs is demonstrated, along with a simulation-based analysis of the PBE behavior. The impact of PBE is investigated by simulation for alternative device architectures, such as bulk FinFETs and FinFETs-on-insulator. PBE is found to be non-negligible in all standard InGaAs FET designs. Practical PBE metrics are introduced and the design of a substrate architecture for PBE suppression is elucidated. Finally, it is concluded that the GAA architecture is not suitable for low-leakage InGaAs FETs; a bulk FinFET is better suited for the role.

We report the fabrication of short-channel FinFETs on InGaAs-on-silicon wafers using the aspect ratio trapping (ART) technique. We demonstrate excellent short-channel control down to 20 nm gate length due to scaled fin width down to 9 nm and reduction of parasitic bipolar effect (PBE). PBE that plagues III-V NFETs with gate-all-around (GAA) or III-V-on-insulator (III-V-OI) structures can be significantly suppressed by optimized ART FinFET technology. We demonstrate record high on-current ION and low drain leakage current for short gate lengths in the 20–32 nm range for InGaAs-on-silicon NFETs.

Ge(1-x)Sn(x) has received a lot of interest for opto-electronic applications and for strain engineering in advanced complementary-metal-oxide-semiconductor technology, because it enables engineering of the band gap and inducing strain in the alloy. To target a reliable technology for mass application in microelectronic devices, the physical problem to be addressed is to unravel the complex relationship between strain relaxation (as induced by the growth of large layer thicknesses or a thermal anneal) and defect formation, and/or stable Sn-cluster formation. In this paper, we study the onset of Sn-cluster formation and its link to strain relaxation using Atom Probe Tomography (APT). To this end, we also propose a modification of the core-linkage [Stephenson et al., Microsc. Microanal. 13, 448 (2007)] cluster analysis method, to overcome the challenges of limited detection efficiency and lateral resolution of APT, and the quantitative assessment for very small clusters (<40 atoms) embedded in a random distribution of Sn-atoms. We concluded that the main relaxation mechanism for these layers is defect generation (misfit dislocations, threading dislocations, etc.), irrespective of the cause (thickness of layer or thermal anneal) of relaxation and is independent of the cluster formation. The low thermodynamic solubility limit of Sn in Ge seems to be the driving force for Sn-cluster formation. Finally, we also discuss the spatial distribution of Sn in clusters and relate them to the theoretically predicted stable Sn clusters [Ventura et al., Phys. Rev. B 79, 155202 (2009)]. (c) 2015 AIP Publishing LLC.

The impact of dopant concentration on the current densities of In0.53Ga0.47As/GaAs0.5Sb0.5 heterojunction Esaki tunnel diodes is investigated. Increased doping density results in increased peak and Zener current densities. Two different structures were fabricated demonstrating peak current densities of 92 kA/cm2 and 572 kA/cm2, Zener current densities of 994 kA/cm2 and 5.1 MA/cm2 at a −0.5 V bias, and peak-to-valley current ratios of 6.0 and 5.4, respectively. The peak current scaled linearly with area down to a 70 nm diameter. The peak current densities were benchmarked against Esaki diodes from other material systems based on doping density and tunnel barrier height.

Extending our previous study demonstrating that ALD-BeO hi-k on Si and III-V exhibits excellent electrical characteristics, we discuss the advantages of using BeO as the interface passivation layer (IPL) in silicon metal-oxide-semiconductor field effect transistors (Si-MOSFETs) from the perspective of the gate-first and the gate-last process. By comparing three hi-k stacks, BeO/HfO2, Al2O3/HfO2, and SiO2/HfO2, fabricated using the gate first and gate last processes, we demonstrate that for both processes, BeO/HfO2 significantly outperforms the other stacks in terms of drive current, transconductance (Gm), subthreshold swing (SS), inversion capacitance, and mobility.

In this paper, we discuss atomic configuration of atomic layer deposition (ALD) beryllium oxide (BeO) using the quantum chemistry to understand the theoretical origin. BeO has shorter bond length, higher reaction enthalpy, and larger bandgap energy compared with those of ALD aluminum oxide. It is shown that the excellent material properties of ALD BeO can reduce interface defect density due to the self-cleaning reaction and this contributes to the improvement of device performance of InGaAs MOSFETs. The low interface defect density and low leakage current of InGaAs MOSFET were demonstrated using X-ray photoelectron spectroscopy and the corresponding electrical results.

A conformal, chemical-based sulfur monolayer doping process (thereafter S-MLD) on InxGa1-xAs (x = 0.53) material is reported. Ultra-shallow junction (xj <; 10 nm) and low sheet resistance Rs <; 200 Ω/ is demonstrated with bulk activation > 80% at sulfur concentration of >1019/cm3.

Instability of InGaAs channel nMOSFETs with the Al 2 O 3 / ZrO 2 gate stack under positive bias stress demonstrates recoverable and unrecoverable components, which can be tentatively assigned to the pre-existing and generated defects, respectively. The recoverable component is determined to be primarily associated with the defects in the Al 2 O 3 interfacial layer (IL), the slow trapping at which is responsible for the power law time dependency of the threshold voltage shift and transconductance change. The fast electron trapping in the ZrO 2 film exhibits negligible recovery, in contrast to the Si-based devices with a similar high-k dielectric film. Generation of new electron trapping defects is found to occur in the IL, preferentially in the region close to the substrate, while trap generation in the high-k dielectric is negligible.

Trap spectroscopy by charge injection and sensing method was applied to the In0.53Ga0.47As-Al2O3 system, yielding the spatial and energetic distribution of the traps inside the Al2O3 layer. The trap density inside the atomic-layer-deposited (ALD) Al2O3 layer was found to be significantly reduced by (NH4)(2)S treatment of the InGaAs surface prior to the Al2O3 deposition. Indium concentration inside the Al2O3 layer was found to be reduced once the InGaAs surface is (NH4)(2)S treated prior to the Al2O3 deposition as measured by time-of-flight secondary ion mass spectroscopy, indicating indium as a possible origin of the oxide traps. The results suggest a new mechanism for the sulfur action at the InGaAs surface, which might be responsible for the transistor performance improvements observed after (NH4)(2)S passivation. This mechanism involves sulfur as an indium diffusion/segregation barrier stabilizing the InGaAs surface during the ALD Al2O3 deposition, lowering the oxide trap density. This, in turn, improves the electron mobility through a reduction in the Coulomb scattering of the carriers due to border traps and improves the device drive current.

III-V tunneling field effect transistors (TFET) for low voltage logic applications (<;0.5V) have gained attention with the demonstration of sub-60 mV/dec. subthreshold slopes [1]. A key outstanding issue with TFETs is limited drive currents, due to non-optimized carrier tunneling. With that issue in mind, the aim of this work is to map III-V Esaki tunnel diode (TD) performance to engineer TDs with ultra high current densities while maintaining large peak-to-valley current ratios (PVCR). This work describes the most comprehensive experimental benchmarking of TD performance reported, including (i) GaAs, (ii) In0.53Ga0.47As, (iii) InAs, (iv) InAs0.9Sb0.1/Al0.4Ga0.6Sb, and (v) InAs/GaSb as a function of doping and effective tunnel barrier height. These results confirm that heterojunctions (bandgap engineering) and doping will enhance peak (JP) and Zener current densities beyond homojunction TDs [3], to a record 2.2MA/cm2 (JP) and 11 MA/cm2 (@ -0.3 V), laying the fundamental groundwork for a III-V TFET at the 7 nm technology node.

A technique is presented to study the electrostatic degradation of key germanium metal-oxide-semiconductor field-effect transistor (MOSFET) performance metrics such as the subthreshold slope SS, the drive current, and the OFF-state current. This is calculated using the superposition of the contributions from individual trap profiles, arising from a piecewise approximation of any arbitrary interface-trap spectrum. A technology computer-aided design simulation using this approach has been directly applied to the electrical evaluation of various scaled Ge p-channel FETs with different passivation schemes. The relative SS degradation due to interface traps is shown to be independent of the gate length, even in scaled devices exhibiting short-channel effects. Additionally, a linear dependence of the relative degradation with an equivalent oxide thickness (EOT) is observed. As such, a transistor's subthreshold performance is less impacted by a given concentration of interface traps, as the EOT is further reduced. Finally, the MOSFET drive current is shown to be degraded due to interface traps, mainly through additional scattering in the channel, while the electrostatic effect is rather small.

CMOS scaling for sub-12 nm nodes will need high-mobility channel semiconductors such as III-V materials to be integrated on large diameter Si substrates. A way to overcome lattice mismatch is to confine defects resulting from strain relaxation on the sidewalls of trenches made by etch-back of Si in standard Shallow-Trench-Isolation (STI) structures. The surface of the InP layers, grown as buffer material in these trenches by selective epitaxy, is planarized by means of CMP, after which it needs to be recessed to allow for the deposition of the III-V channel stack. We have developed an in situ HCl etching process allowing a close control of the recess depth down to a few nm and leaving a clean and planar InP surface well suited for subsequent III-V epitaxial growth. The process development was carried out in a commercial Aixtron Crius MOCVD reactor on standard SiO 2 STI patterned 200 mm Si (001) wafers.

The efficiency of the ammonium sulfide vapor (ASV) treatment, as opposed to the wet treatment in the liquid ammonium sulfide solution, on the performance improvement of the In0.53Ga0.47As surface-channel as well as InP-capped buried-channel metal-oxide-semiconductor field-effect-transistors (MOSFET) was demonstrated for the first time. MOSFETs were fabricated with either HCl or ASV surface treatments prior to the gate oxide deposition. ASV treatment was found to be very efficient in boosting the drive current of the transistors compared to that of the HCl treatment. It was also found that the ASV treatment leads to a lower border trap density and slightly higher oxide/semiconductor interface defect density compared to that of the HCl treatment. X-ray photoelectron spectroscopy (XPS) studies of In0.53Ga0.47As native oxide regrowth after both surface treatments identified indium sub-oxides as a possible cause of the performance degradation of the HCl treated devices. Based on this work, ASV treatment could be an efficient solution to the passivation of III-V surfaces.