Gate-all-around Silicon RibbonFET CMOS transistors at gate length $(\mathrm{L}_{\mathrm{G}})$ of 6nm are demonstrated and comprehensively characterized. Single Nanoribbon (1NR) vehicle disconnected from subfin is developed to accurately evaluate “true” short channel effect and performance as a function of $\mathrm{L}_{\mathrm{G}}$ and Silicon thickness $(\mathrm{T}_{\text{si}})$. NR $\mathrm{T}_{\text{si}}$ scaling demonstrated to improve short channel effect without penalty to performance down to 3nm, below which, surface roughness scattering degrades transport. Effective workfunction engineering is performed to reduce threshold voltage at highly scaled gate length and compensate for threshold voltage increase due to quantum confinement at scaled $\mathrm{T}_{\text{si}}$. Injection velocity $(\mathrm{v}_{\mathrm{x}0})=1.13\mathrm{x}10^{7}\text{cm}/\mathrm{s}$ at $\mathrm{L}_{\mathrm{G}}=6\text{nm}$ with no degradation down to $\mathrm{T}_{\text{si}}=3$ nm is demonstrated. These key highlights pave the path for continued gate length scaling which is one of the key foundational cornerstones of Moore's law.

Process and device simulation has been invaluable for logic technology development for many technology nodes. The main goal of this work will be to review the broad and diverse simulation hierarchy that is used in industry to understand and optimize both current and future device technology options. This hierarchy spans both continuum modeling and atomistic methods / beyond continuum tools. Current process and device simulation results will be presented along possible extensions to the hierarchy to improve TCAD’s ability to help technology development.

TCAD process and device simulation has been used to understand and optimize advanced logic devices for many technology nodes. Stress engineering and modeling has also been an important part of device analysis for decades, long before it was intentionally engineered for transistor performance. Initial stress studies were process-only simulations of stress-dependent silicon oxide growth for isolation [1,2,3,4,5] and were extended to include strain from thermal mismatch, intrinsic, and dopant strain [6,7]. Process and device simulations have also been used to explain increased junction leakage [8] and layout dependent reduced electron mobility [9]. The first intentionally engineered strain sources include nitride capping layers and embedded SiGe S/Ds [10,11]. As technology development has progressed, both the unintentional and engineered strain sources have changed considerably. Device scaling modifies the geometry, which in turn changes the stress from generation to generation. In addition, new technology features and architectures can affect both intentional and unintentional strain sources. This paper reviews how strain sources have changed, how modeling has evolved to simulate the effects of strain in advanced logic devices, and the outlook for engineering strain in future device options. To model stressed devices, both front end process models and stress dependent mobility device models have been developed [12,13]. To evaluate stress effects on device performance requires a process simulator for structure creation, stress and dopant diffusion/activation modeling, and a device simulator that accurately captures the resulting electrostatics as well as carrier mobility and external resistance. In this work, process simulation is performed using an internally modified version of FLOOPS [12,14,15,16,21], while drift diffusion simulations are run with MDS [17] which includes models for stress, orientation and ballisticity on transport [13,18,19,20,22]. The first engineered stress in NMOS employed tensile nitride films over the polysilicon gate [10,11,12,13]. At the 45nm node, HiK and metal gates were introduced, removing the nitride induced stress, but allowing for other strain sources including tensile contact metals and compressive gate metals [23]. In addition, the strain due to edge dislocations in lattice improved NMOS device performance [16]. When trigate transistors were introduced at the 22nm node [24], the strains changed again. From the modeling perspective, trigate devices necessitated both routine 3D simulation [21] and capturing transport in [110] confined channels which changes the mobility response to stress [25]. Poor epitaxial regrowth in the trigate architecture removed edge dislocations as a strain source but allowed for stress from tensile gate metals and also a novel ILD0 [26]. Figure 1 shows stress simulations for different NMOS devices. The main engineered strain source for PMOS devices is embedded SiGe S/Ds. Over time, the Ge fraction was increased while the distance from the SiGe S/D to the channel was decreased [10,11,12,13,17]. In the 45 nm technology node [23], removal of the polysilicon gates increased channel compression [17]. The introduction of trigate devices [24] resulted in the need to capture stress effects on transport in [110]/(110) channels, which has a higher hole mobility but less stress response. Initially there was a concern that the strain from epi S/Ds growth would not be maintained in trigate devices,; however, its effectiveness was later confirmed with TEM measurements [27]. Modeling both edge dislocations [16] and Ge profiles in S/D are important for matching measured strain. Figure 2 shows stress profiles for different PMOS devices. Stress from SiGe S/Ds were also found to exhibit layout effects [28]. This requires simulating stress in an area larger than the device to accurately capture the resulting stress in the channel. Capturing unintentional strain sources, which can easily be overlooked, also makes simulating a larger area critical. For example, ILD0 and gate cut fill strain [29], which occur outside the diffusion box, impact device performance. Future logic device options will involve new materials and architectures which impact device responses to stress and present novel opportunities to engineer strain. New channel materials include sSi for NMOS, sSiGe for PMOS [30], and Ge for NMOS and PMOS [31,32]. Process flow concerns will also evolve, i.e. devices engineered with stress from the substrate will have challenges maintaining stress throughout an epi S/D process and the stress will depend on fin length. Future device architectures include nanowire/nanosheets [33], forksheets [34] and device stacking, which will allow mixing and matching both materials and architectures; examples include combining Ge PMOS nanosheets and Si NMOS finfets [35]. A stress simulation of tensile gate metal for the stacking approach in reference [35] is shown in Figure 3 and illustrates how the same strain source results in different stresses depending on architecture. Figure 1

The observation of room temperature sub-60 mV/dec subthreshold slope (SS) in MOSFETs with ferroelectric (FE) layers in the gate stacks or in series with the gate has attracted much attention. Recently, we modeled this effect in the framework of a FE polarization switching model. However, there is a large amount of literature attributing this effect to a stabilization of quasi-static (QS) negative capacitance (NC) in the FE. The technological implications of a stabilized non-switching (NS) QSNC model vs a FE switching model are vastly different; the latter precluding applications to sub-60 mV/dec SS scaled CMOS due to speed limitations and power dissipated in switching. In this letter, we provide a thorough analysis assessing the foundations of models of QSNC, identifying which specific assumptions (ansatz) may be unlikely or unphysical, and analyzing their applicability. We show that it is not reasonable to expect QSNC for two separate capacitors connected in series (with a metal plate between dielectric (DE) and FE layers). We propose a model clarifying under which conditions a QS "apparent NC" for a FE layer in a FE-DE bi-layer stack may be observed, quantifying the requirements of strong interface polarization coupling in addition to capacitance matching. In this regime, our model suggests the FE layer does not behave as a NC layer, simply, the coupling leads to both the DE and FE behaving as high-k DE with similar permittivities. This may be useful for scaled EOT devices but does not lead to sub-60 mV/dec SS.

Neuromorphic Multiply-And-Accumulate (MAC) circuits utilizing synaptic weight elements based on SRAM or novel Non-Volatile Memories (NVMs) provide a promising approach for highly efficient hardware representations of neural networks. NVM density and robustness requirements suggest that off-line training is the right choice for edge devices, since the requirements for synapse precision are much less stringent. However, off-line training using ideal mathematical weights and activations can result in significant loss of inference accuracy when applied to non-ideal hardware. Non-idealities such as multi-bit quantization of weights and activations, non-linearity of weights, finite max/min ratios of NVM elements, and asymmetry of positive and negative weight components all result in degraded inference accuracy. In this work, it is demonstrated that non-ideal Multi-Layer Perceptron (MLP) architectures using low bitwidth weights and activations can be trained with negligible loss of inference accuracy relative to their Floating Point-trained counterparts using a proposed off-line, continuously differentiable HW-aware training algorithm. The proposed algorithm is applicable to a wide range of hardware models, and uses only standard neural network training methods. The algorithm is demonstrated on the MNIST and EMNIST datasets, using standard MLPs.

Pulse-based studies of ferroelectric capacitor systems have been used by several groups to experimentally probe the mechanisms of apparent negative capacitance. In this paper, the behavior of such systems is modeled through SPICE simulation with a delayed-response Preisach model, and the results are compared to available data. It is found that a simple ferroelectric domain delay model can explain much of the observed behavior, capturing the qualitatively different effects of bipolar and unipolar switching, as well as the voltage dependence of said switching. The observed behavior and its modeling suggests that the observed negative capacitance is in fact associated with ferroelectric switching, and its presence is highly sensitive to the switching frequency and other details of the ferroelectric system.

We demonstrate an SoC logic compatible ferroelectric-metal field effect transistor (FeMFET) digital 2-bit weight cell by monolithic BEOL integration of a ferroelectric (FE) capacitor with the gate of a conventional Si HK/MG MOSFET. Through optimization of the area ratio between the FE capacitor and the MOSFET, we show: 1) program/erase write voltages can be scaled down to logic compatible level, ±1.8 V, simplifying write circuitry; 2) write speed of 100ns; 3) write endurance cycles without degradation due to elimination of charge trapping in FE; 4) 2 bits/cell achieving software levels of accuracy for inference on MNIST training database; 5) state retention approaching 10 4 s for a depolarization field of 0.3 MV/cm; 6) Multi-port (independent read and write) operations.

We report on measurements and modeling of FE HfZrO/SiO2 Ferroelectric-Dielectric (FE-DE) FETs which indicate that many of the phenomena attributed to Negative Capacitance can be explained by a delayed response of ferroelectric domain switching - referred to as Transient Negative Capacitance (TNC). No traversal of the stabilized negative capacitance branch is required. Modeling is used to correlate the hysteretic properties of the ferroelectric material to the measured transient and subthreshold slope (SS) behavior. It is found that steep SS can be understood as a transient phenomenon, present when significant polarization changes occur. The experimental signature of TNC is investigated, and guidelines for detecting it in measured data are outlined. The technological implications of FE polarization switching are investigated, and it is found that NCFETs relying on it are not suitable for high performance CMOS logic, due to voltage, frequency, and hysteresis limitations. Requirements for experimental evidence of stabilized S-curve behavior are summarized.

A multi-bit digital weight cell for high-performance, inference-only non-GPU-like neuromorphic accelerators is presented. The cell is designed with simplicity of peripheral circuitry in mind. Non-volatile storage of weights which eliminates the need for DRAM access is based on FeFETs and is purely digital. The Multiply-and-Accumulate operation is performed using passive resistors, gated by FeFETs. The resulting weight cell offers a high degree of linearity and a large ON/OFF ratio. The key performance tradeoffs are investigated, and the device requirements are elucidated.

We report on measurements and modeling of FE HfZrO/SiO 2 Ferroelectric-Dielectric (FE-DE) FETs which indicate that phenomena attributed to Negative Capacitance can be explained by a delayed response of ferroelectric domain switching. No traversal of the stabilized negative capacitance branch is required. Modeling is used to correlate the hysteretic properties of the ferroelectric material to the measured transient and subthreshold slope (SS) behavior. It is found that steep SS can be understood as a transient phenomenon, present only when significant polarization changes occur. The technological implications of this finding are investigated, and it is found that NCFETs are most likely not suitable for high-performance CMOS logic, due to voltage, frequency, and voltage polarity limitations.

In this letter, we show that conventional III-V MOSFETs with moderate/high In content channels (In0.53Ga0.47As or In0.70Ga0.30As) at scaled nodes are incompatible with mobile SoC designs, which often operate at intermediate/high V-dd (0.7 V to >= 1 V) to achieve high frequency including during burst-mode. The incompatibility is due to conventional III-V FETs having too small bandgap, and thus too high leakage when operated at the increased voltages. We show that FETs with a more optimal lower In content, In0.35Ga0.65As, have the necessary combination of larger bandgap (similar to Si) and sufficiently high injection velocity (similar to 2.5 times Si) to enable both low leakage and high performance (versus Si), across the entire Vdd range of mobile SoC operation. We report for the first time the growth and characterization of ultra-thin In0.35Ga0.65As FETs with a standard 1nm EOT gate dielectric. Calibrated models show that In0.35Ga0.65As enables the highest performance at very low leakages at intermediate/high Vdd in short channel FETs.

InGaAs-based Gate-all-Around (GAA) FETs with moderate to high In content are shown experimentally and theoretically to be unsuitable for low-leakage advanced CMOS nodes. The primary cause for this is the large leakage penalty induced by the Parasitic Bipolar Effect (PBE), which is seen to be particularly difficult to remedy in GAA architectures. Experimental evidence of PBE in In70Ga30As GAA FETs is demonstrated, along with a simulation-based analysis of the PBE behavior. The impact of PBE is investigated by simulation for alternative device architectures, such as bulk FinFETs and FinFETs-on-insulator. PBE is found to be non-negligible in all standard InGaAs FET designs. Practical PBE metrics are introduced and the design of a substrate architecture for PBE suppression is elucidated. Finally, it is concluded that the GAA architecture is not suitable for low-leakage InGaAs FETs; a bulk FinFET is better suited for the role.

Germanium is one of the promising materials for future CMOS technologies, due to its high carrier mobility and low Schottky barrier height (for PMOS). However, the presence of a small direct gap (in addition to the main indirect gap at the L-point) can result in significant band-to-band tunneling (BTBT), even at low voltages. If not remedied, it is easily the dominant BTBT mechanism. In this letter, the dependence of BTBT on the alloy composition in Ge-rich SiGe is studied using detailed simulation of the bandstructure. It is shown that even a very low stoichiometric fraction of Si in a FinFET results in a dramatic reduction of direct BTBT, much more so than in a corresponding p-i-n diode.