The phenomenon of dopant dose loss through trapping at the Si–SiO2 interface has important consequences for metal–oxide–semiconductor device fabrication. It represents also a challenge to analytical techniques, since the trapped dopants appear to exist in one or a few monolayers thickness at the interface. In this work, we report on a complementary approach, using both electrical device data and accurate process modeling, as well as analytical dopant profiling with secondary ion mass spectroscopy, to investigate important features of the phenomenon, such as dose dependence, detrapping, and transient enhanced diffusion effects. This approach enabled the development of dose loss models suitable for design of current and future complementary metal–oxide–semiconductor technologies.

Large area capacitors were fabricated with doping and oxide thickness representative of an n-MOSFET channel region. Capacitance–voltage (C–V) measurements on these capacitors showed a systematic change in the accumulation capacitance when additional implant damage is introduced by a 1×1014 cm−2 40 keV silicon implant. The oxide thickness values extracted from the C–V data increase by 1–4 Å with the additional implant damage. This trend is confirmed by additional high resolution TEM and X-ray reflectivity measurements. We postulate that the implant damage increased the oxidation rate, due either to the interstitial flux during TED, or to an increase in surface roughness. For channels doped with boron implantation, the increase in thickness does not change with a 5× increase in the doping dose. In contrast, with BF2-implanted channels, the effects are smaller for higher doping dose.

The phosphorus dose loss by trapping at the Si-SiO2 interface was studied for the various process modules of a 0.3 µm CMOS technology, both separately and in combination. SIMS measurements showed significant dose loss, up to 30%, and also a sizable de-trapping after a 1000°C anneal. The de-trapping was observed as an additional peak at the silicon surface. A new model which includes both trapping and de-trapping phosphorus fluxes was incorporated into the process simulator PROPHET. Subsequently, simulations were able to reproduce the SIMS data as well as NMOS threshold voltage values. The model also showed that the dose loss is enhanced by TED, thereby explaining the measured dependence of the dose loss on the implanted dose, and the fact that the major dose loss in the CMOS process occurred during the first anneal after implantation.

A model for the phosphorus dose loss effect is developed and incorporated into the process simulator PROPHET. The dose loss model is applied consistently with the Transient Enhanced Diffusion and the segregation models in PROPHET to provide doping profiles used by the device simulator PADRE in simulations of NMOS, PMOS, and isolation structures for actual VLSI technologies. Comparison of the simulated and measured device characteristics and their dependence on substrate bias and structure geometry shows good agreement, and furthermore highlights the importance of the dose loss phenomenon in these structures.