We scale down transistors in each successive technology generation to increase circuit speed and to improve packing density. However, as scaling continues beyond the 0.1 /spl mu/m technology generation, concerns about three issues, reliability, leakage and mobility degradation, must be addressed. This paper summarizes the current understanding regarding these issues, and identifies areas on which device scaling research could focus.

The present status of computational models for oxide reliability and their success in interpreting the experimental data are reviewed. We find that significant progress has been made in theoretical modeling of all aspects of reliability, and this understanding of the underlying degradation mechanism allows continued oxide scaling beyond the limits previously assumed possible.

SUMMARY In this paper we report on the modeling and simulation of tunneling current in MOS devices including quantum mechanical effects. The simulation model features an original scheme for the self-consistent solution of Poisson and �

The narrowest feature of an integrated circuit is the silicon dioxide gate dielectric (3–5 nm). The viability of future CMOS technology is contingent upon thinning the oxide further to improve drive performance, while maintaining reliability. Practical limitations due to direct tunneling through the gate oxide may preclude the use of silicon dioxide as the gate dielectric for thicknesses less than 1.3 nm, however.

The question of oxide scaling below 2 nm for CMOS applications is considered both theoretically and experimentally. Based on detailed analysis, we find no intrinsic reliability limits for oxide films as thin as 1.4 nm. However, many manufacturing and processing issues must be resolved before widespread usage of these hyperscaled oxides becomes a reality.

A comprehensive percolation model is used to explore the role of non-uniform trap generation process on oxide breakdown. We show that this non-uniform trap generation (due to SILC and roughness induced localization) makes interpretation of experimental data difficult and can lead to incorrect projections for reliability of ultra-thin oxides.

A simple theory of soft breakdown, that can explain wide ranging experimental data, is proposed. In addition, this model identifies the appropriate conditions for which soft breakdown turns into hard breakdown and the origin of bimodal failure distribution. Connections to older theories for thicker oxides are established and consequences of the new theory for the reliability of ultra-thin gate oxides are analyzed.

Large area capacitors were fabricated with doping and oxide thickness representative of an n-MOSFET channel region. Capacitance–voltage (C–V) measurements on these capacitors showed a systematic change in the accumulation capacitance when additional implant damage is introduced by a 1×1014 cm−2 40 keV silicon implant. The oxide thickness values extracted from the C–V data increase by 1–4 Å with the additional implant damage. This trend is confirmed by additional high resolution TEM and X-ray reflectivity measurements. We postulate that the implant damage increased the oxidation rate, due either to the interstitial flux during TED, or to an increase in surface roughness. For channels doped with boron implantation, the increase in thickness does not change with a 5× increase in the doping dose. In contrast, with BF2-implanted channels, the effects are smaller for higher doping dose.

One of the primary means for improving performance and increasing the scale of integration on a chip is the miniaturization of the electronic devices that comprise it. The SIA roadmap projects that future gains in performance will continue to accrue from this approach. One of the guiding principles for miniaturization has been the scaling of successful existing device designs to smaller dimensions. While there may be no compelling reason why the SIA targets cannot be achieved by continued scaling, an accurate assessment of the limiting performance that can be derived from conventional CMOS is crucial for identifying the principal impediments and for developing alternatives. Here, we identify five impediments that we have encountered as we attempt to scale CMOS technology toward 10 nm gate lengths: optical lithography, gate oxide tunneling, enhanced boron diffusion in the ultra-shallow junction, drive current saturation with decreasing oxide thickness, and the subthreshold current.

Reports measurements of the DC characteristics of sub-100nm pMOSFETs that employ low leakage, ultra-thin gate oxides only 1-2nm thick and ultra-shallow junctions to achieve high current drive capability and transconductance. We demonstrate that I/sub Dsct/=0.23mA//spl mu/m can be achieved with a L/sub x/=65nm physical gate length at 15V using a 1.5nm gate oxide with a gate leakage current less than 20nA//spl mu/m/sup 2/ on devices without silicided contacts. But more importantly, we find no evidence of boron penetration through SiO/sub 2/ gate oxides as thin as 1.3nm, grown at 1000C using rapid thermal oxidation (RTO). Furthermore, for the first time, we have directly imaged the ultra-shallow p-n junctions that comprise a sub-100nm pMOSFET with an effective channel length of 20nm to show that the lateral extent of the junction is approximately half that of the vertical junction depth. We surmise that the enhanced vertical diffusion has an adverse effect on subthreshold characteristic of sub-100nm pMOSFETs.

Results are described for a gate level technology module developed to produce metal–oxide–semiconductor transistors with physical gate lengths of 70 nm and below. Lithography is performed by direct write e-beam lithography (EBL) using a thermal field-emission EBL system in SAL 601 resist. Critical dimension (CD) control, as measured by several methods, is found to depend not only on dose control but also on writing parameters such as pixel spacing. The pattern transfer using a silicon dioxide hard mask is shown to exhibit a trade-off between anisotropy and selectivity. Transmission electron microscopy cross sections reveal that two atomic layers are removed even when the gate oxide stopping layer is completely intact. We report results for gate lengths down to 60 nm with edge roughness on the order of 5 nm, within the acceptable limits for threshold requirements, while stopping the etch process on oxides as thin as 1.2 nm.

Reports measurements of the DC characteristics of sub-100 nm nMOSFETs that employ low leakage ultra-thin gate oxides only 1-2 nm thick to achieve high current drive capability and transconductance. We demonstrate that I/sub Dsat//spl ap/1.8 mA//spl mu/m can be achieved with a 60 nm gate at 1.5 V using a 1.3-1.4 nm gate oxide with a gate leakage current less than 20 nA//spl mu/m/sup 2/. Furthermore, we find that I/sub Dsat/ deteriorates for gate oxides thicker or thinner than this.