We discuss the engineering and physics of both Si MOS and Si/SiGe quantum well based spin qubit devices fabricated in a process compatible with CMOS high volume manufacturing. This includes new process innovations around buffer engineering, EUV lithography for gate pitch scaling, and the creation of a fully electrostatically defined planar quantum dot flow not requiring STI for confinement. Charge sensing, tunnel coupling, and valley splitting are characterized down to the single electron limit for both systems. The gate dielectric interface quality is correlated to potential landscape control and spurious dot formation. While coherent control of spin is demonstrated in both systems with comparable gate fidelity (>99.1%) and coherence times (> 1ms), the scaling challenges are very different, with Si MOS requiring dielectric interface Dit improvements for spurious dot reduction and the Si/SiGe system requiring improvements to valley splitting.

This paper presents key specifications of RRAM-based nonvolatile memory embedded into Intel 22FFL FinFET Technology. 22FFL is a high performance, ultra low power technology developed for mobile and RF applications providing extensive high voltage and analog support and high design flexibility combined with low manufacturing costs [1]. Embedded RRAM technology presented in this paper achieves 10 4 cycle endurance combined with 85°C 10-year retention and high die yield. Technology data retention, endurance and yield are demonstrated on 7.2Mbit arrays. We describe device characteristics, bit cell integration into the logic flow, as well as key considerations for achieving high endurance and retention properties.

This paper presents key features of MRAM-based non-volatile memory embedded into Intel 22FFL technology. 22FFL is a high performance, ultra low power FinFET technology for mobile and RF applications with extensive high voltage and analog support, and a high level of design flexibility at low cost 1 . Embedded NVM technology presented here achieves 200°C 10-year retention capability combined with>10 6 cycle endurance and high die yield. Technology data retention, endurance and yield capabilities are demonstrated on 7.2Mbit arrays. We describe device-level MTJ characteristics, key integration features, cell characteristics, array operation specifics, as well as key yield milestones.

The impact of silicon technology scaling trends and the associated technological innovations on RF CMOS device characteristics are examined. The application of novel strained silicon and high-k/metal gate technologies not only benefits digital systems, but significantly improves RF performance. The peak cutoff frequency (f(T)) doubles from 209 GHz in the 90 nm node to 445 GHz at the 32 nm node. 1/f flicker noise reduces by an order of magnitude from the 0.13 um node to the 32 nm node. Transistor noise figure, high voltage tolerance, and quality factors of RF passives all show similar benefits from technology scaling.

Record breaking RF performance was recently achieved on a 65nm CMOS technology (29nm L gate , 210nm pitch) employing uni-axial strained silicon transistors. These highest-reported cutoff frequencies for NMOS transistors achieve f T /f MAX values of 360 GHz/420 GHz. PMOS transistors also demonstrate superior performance with f T /f MAX values of 238 GHz/295 GHz. Varactor performance on this substrate technology is also discussed