In this work, the influence of different surface roughness and surface treatments on the minimum energy density required to form low-ohmic nickel contacts on n-type 4H-SiC by laser annealing was investigated. The annealing was performed by a frequency-tripled Nd:YVO 4 laser with a pulse duration of 50 ns. To evaluate the effects, the grinded or polished C-side of 4H-SiC wafers with surface roughness between 0.3 and 70 nm was sputter-deposited with nickel and subsequent laser annealed. Sheet resistance measurements showed that the minimum energy density required to achieve a low-resistance contact depends significantly on the surface roughness. The rougher the surface, the lower the minimum energy density to form a low-ohmic contact.

In this work, an empirical model of structural and material composition of low-ohmic nickel silicide contact formation on n-type 4H-SiC by laser annealing as well as by RTA is presented. For this purpose, systematic studies with different annealing parameters were performed. The development of the empirical model is based on results from characterization of the nickel silicide by FIB-SEM, TEM, XRD analysis as well as electrical characteristics received from 4-point-measurements.

Contamination control is essential in semiconductor manufacturing to ensure high yield and product quality. Latest power electronic devices are manufactured in fully automated 300 mm production lines, which utilize closed wafer containers called Front Opening Unified Pods (FOUPs). It has been observed, that FOUPs capture airborne molecular contaminants (AMC) outgassing from processed wafers or being transferred from the equipment minienvironment. These AMC might be released afterwards and can lead to defects causing yield and/or reliability issues of the power devices. Specific FOUP cleaning and exchange rules are already being utilized in the fab. But so far, these rules are not validated or adapted by actual concentration values in the FOUPs. In this paper, contamination levels in FOUPs are investigated to identify the sources of different AMC. The contamination data is analysed together with FOUP logistics data in order to establish an optimized FOUP management strategy. In the first part, in-line carrier contamination control is explained and a general overview of the AMC detected is given. In the second part, the data-driven FOUP-monitoring is described using the example of the root cause analysis of hydrofluoric acid (HF) contamination.

In this work, pulsed-laser-based tempering was applied for post-implant annealing of n-type N-doped 4H-SiC in order to electrically activate the dopants and to rebuild the crystal structure. The annealing was performed by a frequency-tripled Nd:YVO 4 laser with a pulse duration of 60 ns. To evaluate the effects of post-implant annealing, JBS diodes were electrically characterized. The results were compared with implanted, not post-annealed JBS diodes. The electrical measurements showed a significant on-state voltage drop of 40 mV at 6 A for post-implant laser annealed diodes compared to not post-implant annealed diodes.

The compensation of charge carriers is an important aspect to be considered in Aluminum doped areas in 4H-SiC. In this paper, a straightforward method has been found to implement compensation effects into a basic device simulation model and to improve the conformance of electrical measurement and simulation results. By implementing the compensation factors, which depend on Aluminum doping concentration, device simulation in combination with basic device cell structure can be used to create electrical characteristics that are in accordance with measured characteristics. This is a simple alternative for complex process simulation, taking into account physical effects like defects in the crystal structure. The method was used for simulation of lateral MOSFETS transfer characteristic as well as VDMOS blocking characteristic. Found compensation values were 80 % in the 1.5 ∙ 10 17 cm - 3 Al-doped channel region and 23% in the deep, 7.5 ∙ 10 1 7 cm - 3 Al-doped, shielding region.

In this work, the impact of channel implantations (IMP) on the electrical characteristics of SiC n-and p-MOSFETs and analog SiC-CMOS operational amplifiers (OpAmp) is investigated. For this purpose, MOSFETs and Miller OpAmps with and without IMP were fabricated and electrically characterized from room temperature up to 350°C. For devices with IMP the absolute values of the threshold voltages of n-and p-MOSFETs were reduced by 1.5 V and the mobility of the n-MOSFET was increased from 13 to 23 cm2/Vs whereas the mobility of the p-MOSFET remained constant at 6 cm2/Vs. For the resulting OpAmp with IMP, the common-mode input voltage range as well as the open loop gain was increased by 1.5 V and 4 dB compared to non-implanted devices. This improvement was observed across the entire analyzed temperature range from room temperature up to 350°C.

In this work, the influence of pre-deposition interfacial oxidation or post-deposition interface nitridation on the performance of 4H-SiC MOS capacitors was investigated. The gate oxide was deposited by LPCVD using TEOS as a precursor. Interface breakdown strength was derived from leakage current and Time-Zero Dielectric Breakdown characteristics whereas interface quality was assessed by the determination of interface state density from the comparison of quasi-static and high frequency capacitance-voltage characteristics using high-low method. In the experimental results, it is demonstrated that the gate oxide deposited by LPCVD using TEOS which is post-deposition annealed in nitric oxide ambient is advantageous for trench-gate MOSFET due to its effectiveness for improving the interface quality and oxide reliability, whereas pre-deposition interfacial oxidation is deleterious to interface state density and breakdown strength.

In this article, we report the experimental results of a visible-light-blind 4H-polytype silicon carbide phototransistor able to detect ultraviolet (UV) radiations for wavelengths lower than 380 nm with a significative improvement in the optical gain compared with the state-of-the-art of 4H-SiC UV phototransistors. From the electro-optical measurements, the device shows a dark current of 0.62 pA, an ON-/OFF-current ratio of seven orders of magnitude up to bias voltage of -0.5 V, and an excellent optical gain of 1.14.10(5) at 300 nm, whereas it is only 2.6.10(-3) at 400 nm demonstrating a good rejection of visible radiations. Besides having high optical gain, the phototransistor is also more sensitive than the conventional 4H-SiC UV detectors for wavelengths with low penetration depths, because its structure is designed to have the electric field up to the radiated surface where the photogenerated electron-hole pairs are efficiently swept up before recombination occurs. The operating principle of the detector is also investigated, and we experimentally proved that differently from the conventional 4H-SiC bipolar junction transistor phototransistor, it is based on the change in the potential barrier height, which controls the current flow, due to the variation in the Fermi levels when the electron-hole pairs are photogenerated. A comparison with the state-of-the-art of 4H-SiC UV phototransistors is reported.

In this study, UV Photoluminescence (UVPL) and Differential Interference Contrast (DIC) mapping was applied for process control of a 1.2 kV 4H-SiC VDMOS fabrication process at different process stages in order to investigate the influence of shallow pits on the electrical behavior of the devices. In particular, it could be shown that UVPL and DIC mapping allows the correlation of shallow pits and the occurrence of darker regions in the UVPL images and distinguishing differently implanted regions at distinct process stages. By comparing the darker regions of the UVPL scan with the electrical blocking characteristics of the associated devices a direct correlation between the occurrence of shallow pits and the reduction of the blocking capability of the devices could be observed.

The possibility to analyze micrometer scaled 2D implantation profiles is essential for improving SiC power devices. Due to the fact that the oxidation rate depends on the doping concentration a rather simple method was developed in order to decorate highly doped (aluminum) implantation profiles. For this purpose, different samples were grinded with a shallow bevel angle and subsequently oxidized. It could be shown that this method allows analyzing the implantation depth of different box-shape implanted samples. Furthermore the ability to distinguish micrometer scaled 2D profiles for a state-of-the-art SiC power device could be shown.

Production yield is a major factor for semiconductor device manufacturing. To produce high performance devices cost efficiently, it is important to know the process windows of the implemented production technology. This can influence the yield in different ways. One of the critical steps is the photolithography. In this work the impact of misalignment within the technological limits is analyzed and discussed. 4H-SiC VDMOS Transistors were produced and the electrical characteristics were compared with the overlay accuracy of the devices. Small change in channel length can lead to large impact on the electrical characteristic. Especially when the channel length reaches values near to the critical length for short channel effects (SCEs), small overlay inaccuracies influence the electrical characteristic of the devices in an increasing manner. Different cell designs were analyzed regarding their robustness to misalignment.

A comparison between self-aligned process (using lift-off) and Ni-SALICIDE used in fabrication of ohmic contacts for SiC Power MOSFET is done. Both processes are demonstrated for 3.3 kV SiC VDMOS transistors fabricated on 100 mm substrates. It is shown that the Ni-SALICIDE process with first silicidation at 500 °C does not degrade the electrical properties of silicon dioxide; particularly, a degradation of the interlayer dielectric between source and gate is not evident. Additionally, this first silicidation is found to have a positive impact on the specific resistance of contacts formed on p-type SiC using NiAl2.6% as an ohmic metal.

In this work, the ohmic contact mechanism of Ni electrodes on C-faced 4H- n -SiC was investigated by evaluating the electrical and microstructural properties in the contact interface as a function of annealing temperatures ranging from 950 to 1100°C. We determined that Ni-silicide, especially the NiSi phase, plays a key role in the formation of ohmic contacts rather than an increase in carbon vacancies in the C-faced SiC substrate. A vertically oriented NiSi phase was observed in the thermally annealed sample at the optimized temperature that behaves as a current path. A further increase in annealing temperature leads to the degradation of ohmic behavior due to the formation of horizontal-type NiSi in the Ni-rich Ni-silicide/NiSi/SiC structure.

In this work, monolithically integrated wavelength-selective 4H-SiC UV-sensor arrays were manufactured using two photolithography masks and only one implantation sequence demonstrating the potential of the advanced 4H-SiC process technology for the first time. The process technology is described in detail for the fabrication of a 2 x 2 wavelength-sensitive UV-sensor array including two variants with different thicknesses of the p-emitter. The maximum spectral responsivity is 92 mA/W for a wavelength of 300 nm and the devices with a thick p-emitter and 162 mA/W for a wavelength of 290 nm and devices with the thin p-emitter. The corresponding values of the external quantum efficiency are 38%, and 69%, respectively. Furthermore, another UV-sensor characteristic is found evaluating the current difference between both types with a maximum spectral responsivity of 80.2 mA/W at a wavelength of 270 nm.

In this paper we report on the performance of 4H-SiC bipolar diodes as temperature sensors far beyond 273K. The sensor is measured from 150K to 445K covering a temperature range of 295K. In this operating temperature range, the sensor characteristic VD-T is highly linear and it is dominated by the typical dependence of the p-i-n diode voltage on the temperature. The sensor sensitivity is -4.48mV/K for a diode current of 2nA with a maximum error of 4.3K across the full temperature range. Although 4H-SiC p-i-n are mainly focused on very high temperature applications, our analysis on the performance of bipolar diodes at low temperatures highlights its feasibility as temperature sensor for aerospace and high altitude applications where cryogenic temperatures are achieved.

In this work, the impact of a shallow aluminum channel implantation on the channel properties of SiC p-MOSFETs and digital SiC CMOS devices is investigated. For this purpose, p-MOSFETs, CMOS inverters and ring oscillators with different channel implantation doses were fabricated and electrically characterized. The threshold voltage of the resulting p-MOSFETs was shifted from-5 V to-3.6 V whereas the effective channel mobility was slightly decreased from 11.8 cm2/Vs to 10.2 cm2/Vs for a p-MOSFET channel implantation dose of 2∙10 13 cm -2 compared to the non-implanted channel. The resulting p-MOSFETs enable SiC CMOS logic circuits to operate with a 5 V power supply and to satisfy 5 V TTL input level specification over the whole temperature range of 25°C to 400°C. Furthermore the propagation delay time of inverters was reduced by 80% at 25°C and 40% at 400°C compared to inverters without p-MOSFET channel implantation.

In this paper the Bipolar Mode Field Effect Transistor (BMFET) is demonstrated for the first time in 4H-SiC. The structure is based by two p + -type regions symmetrically placed at both sides of a n-type region channel and the device implements two control mechanisms: into the channel the potential barrier controls the electron flow in the off-state operations, like VJFET-based devices, whereas, during the on-state, the holes injected from the p-n junctions induce the conductivity modulation of the channel reducing the on-resistance with beneficial effects on current gain and switching operations. In order to avoid the reduction of carrier lifetime into the channel due to ion implantation and trench etching, an ad-hoc fabrication process has been set-up to enable the conductivity modulation into the channel. First experimental tests on the prototypes show the correct operations of the device as demonstrated from the changing of the output characteristic from triode-like to pentode-like behaviors, which are ascribed to the two main operation principles of the device.

For the first time, we report on the performances of 4H-SiC p-i-n-diode temperature sensors for operating temperatures between 20.5 and 802 K. In this huge temperature range, three ranges of performance were identified with the limit temperatures at 78.2 and 176.3 K. In each of these ranges, a different dominant current transport mechanism is shown and in this paper, a detailed analysis and discussion are reported. The sensor performances were extracted from VD-T characteristics at different fixed ID values. In particular, at ID = 1 μA and in the temperature range between 78.2 and 802 K, we found a sensor sensitivity of 2.3-3.4 mV/K with a rms temperature error, eT, of less than 4.2 K and the sensor shows an excellent linearity-quantified by the coefficient of determination R 2 higher than 0.9993. For even lower temperatures (below 78.2 K), low measurement currents like 10 nA are required leading to a sensitivity of 5.8 mV/K, but a lower linearity (R 2 = 0.9095) and an rms temperature error of 9.7 K which makes the sensor only partially usable in the temperature range between 20.5 and 78.2 K. Finally, the sensor performances are compared with other state-of-the-art solutions.

Carefully designed 4H-SiC Junction Barrier Schottky diodes are capable of the low on-state losses and surge current ruggedness required to be employed as freewheeling diodes in wind turbine generators. Ion implantation is a crucial process step for the performance of such JBS diodes. To better understand the influence of the implantation on the forward characteristics, JBS and Schottky diodes were fabricated and characterized. The measurement data was compared with TCAD models. Monte Carlo simulations were used to accurately model the implantation including lateral straggling and channeling. The simulations show that the actual junction barrier spacing is reduced by 1 µm in the manufactured device compared to the intended spacing. Schottky region pinch-off which occurs at a spacing of less than 3 µm must be avoided.