Crossbars are a basic building block of networks on chip that can be used as fast, single-stage networks or in router cores for larger scale networks. However, scaling crossbars to high radices presents a number of efficiency, performance, and area challenges. Thus, we propose modular flow-through crossbar switch cores that perform better at high radices than conventional monolithic designs. The modular sub-blocks are arranged in a controlled flow-through, pipelined scheme to eliminate global connections and maintain linear performance scaling and high throughput. Modularity also enables energy savings via deactivation of unused I/O wires. Evaluation using an analytical crossbar switch modeling tool demonstrated improved energy delay product (up to 5.3X) compared to conventional crossbar switches, but with approximately 30% area overhead. Further, we evaluated modular crossbar networks with the proposed switch cores using BookSim2, cycle-accurate detailed network on chip tool. The proposed design achieves more than 90% saturation capacity with an internal speed up of 1.5, supports data line rates as high as 102.4Gbps (in 40nm CMOS bulk), and offers lower average network latency compared to conventional crossbars.

As process technologies have scaled, the increasing number of processor cores and memories on a single die has also driven the need for more complex on-chip interconnection networks. Crossbar switches are primary building blocks in such networks-on-chip, as they can be used as fast single-stage networks or as the core of the router switch in multi-stage networks. While crossbars offer non-blocking, single-hop, all-to-all communication, they tend to scale poorly with the number of nodes due to the latency and energy of the long wires and high-radix multiplexor structures needed. To combat these limitations, we propose a low-swing crossbar design that uses capacitively driven wires and capacitively coupled multiplexers. Capacitively driven wires offer low swing signaling, higher bandwidths, and low energy consumption, while capacitively coupled multiplexers offer reduced parasitic loading from the inactive inputs. We present a 16×16 64b low-swing crossbar switch designed in a TSMC 40nm CMOS bulk process. Post-layout simulation shows it operating at a maximum frequency of 2.2GHz, achieving a bandwidth of 2.56Tb/s at 0.9V (nominal Vdd) with an area of 0.94mm2. Total energy consumption for full, half, and minimum bandwidths are 110pJ, 84pJ, and 64pJ respectively, thus offering an efficiency of 10.49 Tbps/W, a 3X improvement over previously published results.

We report on a packaged prototype of a WDM photonic transceiver. It is an all-solid state hybrid assembly based on 130nm SOI photonic circuitry integrated with a 40nm CMOS VLSI driver. Our prototype supports eight tunable WDM channels operating at 10Gb/s, each capable of both transmitting and receiving data on the same chip. We discuss two options to close the link using the optical fiber or a waveguide bridge chip. We provide integration details and supporting link measurement data to describe packaged photonic module and its power efficient functionality with its on-chip power per channel averaging 1.3pJ/bit, excluding off-chip laser electrical power.

We present the packaging of a large multi-chip energyefficient WDM silicon photonic interconnect prototype enabled by hybrid integration, high-accuracy optical alignment and thermal-mechanical aware design and assembly.

We describe a multiwavelength hybrid-integrated solid-state link on a 3 µm silicon-on-insulator (SOI) nanophotonic platform. The link spans three chips and employs germanium-silicon electroabsorption waveguide modulators, silicon transport waveguides, echelle gratings for multiplexing and demultiplexing, and pure germanium waveguide photo-detectors. The 8λ WDM Tx and Rx components are interconnected via a routing "bridge" chip using edge-coupled optical proximity communication. The packaged, retimed digital WDM link is demonstrated at 10 Gb/s and 10(-12) BER, with three wavelength channels consuming an on-chip power below 1.5 pJ/bit, excluding the external laser power.

The crossbar is a popular topology for on-chip networks that offers non-blocking connectivity and uniform latency. However, as the number of nodes increases, crossbars typically scale poorly in area, power, and latency/throughput. To better understand the design space, we have developed an on-chip crossbar modeling tool based on analytical models calibrated using circuit-level simulation results in 40nm CMOS. We present a design space exploration showing how crossbar area, power, and performance vary across input/output node number, data width, wire parameters, and circuit implementation. Using the modeling results, we identify a design point that demonstrates 2X higher throughput, 1.4X lower power and 1.2X lower area compared to previous published designs.

In this work we report on a packaged prototype of a WDM photonic transceiver. It is a hybrid assembly based on a 130 nm SOI photonic circuitry integrated with a 40 nm CMOS VLSI driver. Our prototype supports eight tunable WDM channels operating at 10 Gb/s each capable of both transmitting and receiving data on the same chip. We discuss two options to close the link while using the optical fiber or another waveguide bridge chip. We provide hybridization details and supporting link measurement data to describe packaged photonic module and its power efficient functionality as its on-chip power per channel averaged 1.3pJ/bit, laser electrical power excluded.

We report the first complete 10G silicon photonic ring modulator with integrated ultra-efficient CMOS driver and closed-loop wavelength control. A selective substrate removal technique was used to improve the ring tuning efficiency. Limited by the thermal tuner driver output power, a maximum open-loop tuning range of about 4.5nm was measured with about 14mW of total tuning power including the heater driver circuit power consumption. Stable wavelength locking was achieved with a low-power mixed-signal closed-loop wavelength controller. An active wavelength tracking range of > 500GHz was demonstrated with controller energy cost of only 20fJ/bit.

We demonstrate the first germanium-silicon C-band electro-absorption based waveguide modulator array and echelle-grating-based silicon wavelength multiplexer integrated with a digital CMOS driver circuit. A 9-channel, 10Gbps SiGe electro-absorption wavelength-multiplexed modulator array consumed a power of 5.8mW per channel while being modulated at 10.25Gbps by 40nm CMOS drivers delivering peak-to-peak voltage swings of 2V, achieving a modulation energy-efficiency of ~570fJ/bit including drivers. Performance up to 25Gbps on a single-channel SiGe modulator and CMOS driver is also reported.

We report an ultra-low power 100Gbps silicon photonic WDM transmitter tunable with off-chip laser sources. The hybrid CMOS transmitter consists of eight 12.6Gbps WDM channels and consumes a total on-chip power of 33mW.

Optical interconnects play an integral role in large-scale digital computing, switching, and routing systems. The authors describe a path toward future many-chip modules based on silicon photonic interposers that stitch together tens of chips in a dense and efficient communication infrastructure. They review the guiding design principles for this "macrochip" and describe its canonical energy, loss, and area budgets.

We report on a hybrid assembly combining 40 nm bulk CMOS transmitter circuits, 130 nm SOI optical ring modulators, and off-chip lasers. Silicon resistors in the rings enable circuit-based thermal tuning to overcome process variations, resulting in eight 12.6 Gbps channels operating simultaneously at eight different wavelengths. Not counting laser power but including all transmitter circuits, integration parasitics, and static thermal control, the TX array consumes a total of 33 mW, resulting in a net per-channel efficiency of 330 fJ/b.

High-speed data transceiver circuits employ several techniques for dealing with noise, such as using differential architectures. However, under certain circumstances, a transceiver's dominant noise can be bounded and band-limited; and in those cases simpler noise cancellation circuits may suffice. For such transceivers we have designed a tracking circuit to effectively suppress noise. In a 40 nm CMOS technology the tracking circuit consumes a 37% power overhead over a baseline receiver.

We describe transmitter and receiver circuits for a 10-Gbps single-ended optical link in a 40-nm CMOS technology. The circuits are bonded using low-parasitic micro-solder bumps to silicon photonic devices on a 130-nm SOI platform. The transmitter drives oval resonant ring modulators with a 2-V swing and employs static thermal tuners to compensate for optical device process variations. The receiver is based on a transimpedance amplifier (TIA) with 4-kΩ gain and designed for an input power of - 15 dBm, a photodiode responsivity of 0.7 A/W, and an input extinction ratio of 6 dB. It employs a pair of interleaved clocked sense-amplifiers for voltage slicing and uses a DLL with phase adjustment for centering the clock in the data eye. Periodic calibration allows for adjustment of both voltage and timing margins. At 10 Gbps, the transmitter extinction ratio exceeds 7 dB and, excluding thermal tuning and laser power, it consumes 1.35 mW. At the same datarate, the receiver consumes 3.95 mW. On-chip PRBS generators and checkers with 2 31 -1 sequences confirm operation at a BER better than 10 -12 .

We report on a 10-Gb/s digital-to-digital CMOS silicon photonic link with a 2.1-pJ/bit on-chip energy efficiency, using a photon energy of 1.4-pJ/bit and 680-fJ/bit transceivers that integrate 130-nm SOI CMOS photonic devices with 40-nm bulk CMOS circuits.

Silicon photonic interconnects offer a promising solution to meeting the ever growing demand for more efficient I/O bandwidth density. We report an ultralow power 80 Gb/s arrayed silicon photonic transceiver for dense, large bandwidth inter/intrachip interconnects. Low parasitic microsolder-based hybrid bonding enables close integration of silicon photonic array devices optimized on a 130 nm silicon-on-insulator CMOS platform with CMOS very large scale integration circuits optimized on a 40 nm silicon CMOS platform to achieve unprecedented energy efficiency. The hybrid CMOS transceiver consists of eight 10 Gb/s channels with a total consumed power below 6 mW/channel. The eight-channel wavelength division multiplexing transmitter array using cascaded tunable ring modulators demonstrated better than 100 fJ/bit energy efficiency for 10 Gb/s operation excluding the laser power and tuning power, while the eight-channel receiver array using broadband Ge p-i-n waveguide detectors show sensitivity of better than -15 dBm for a bit error rate of 10 -12 at a data rate of 10 Gb/s with energy efficiency of better than 500 fJ/bit.

We report a complete 10Gbps digital CMOS photonic direct chip-to-chip link. The link includes power supply regulation and digital retiming and uses record-low 680 fJ/bit transceivers and an optical power of 1.4 pJ/bit.