In this work, thermo-mechanical stresses and reliability of 3D die-stack structures developed for the Hybrid Memory Cube (HMC) technology are investigated using experiments and modeling analysis. Synchrotron x-ray micro-diffraction measurements are used to directly measure the stress distribution around Cu vias in different die levels. High resolution stress mappings are obtained and verified by finite element analysis (FEA). The FEA is applied to estimate the stress effect on device mobility changes and the warpage of the integrated structure.

Three-dimensional (3D) integration has emerged as a potential solution to the wiring limits imposed on chip performance, power dissipation, and packaging form factor beyond the 14 nm technology node. In 3D integrated circuits (ICs), the through-silicon via (TSV) is a critical element connecting die-to-die in the integrated stack structure. The thermal expansion mismatch between copper (Cu) vias and silicon (Si) can induce complex stresses in TSV structures to drive interfacial failure and Cu extrusion, degrading the performance and reliability of 3D interconnects. This article reviews current studies on thermal stresses and their effects on reliability of TSV structures. Recent results from measurements of stress and plasticity characteristics of Cu TSV structures are reviewed, including wafer curvature, micro-Raman spectroscopy, and synchrotron x-ray microdiffraction techniques. The effects of the Cu microstructure on stress and reliability, particularly on via extrusion and the device keep-out zone in TSV structures, are discussed. Based on the analysis of the reliability impact, we explore the potential of material and processing optimization to build reliable TSV structures for 3D ICs.

This study investigates the effect of grain boundary sliding (GBS) and material properties on the extrusion of through-silicon via. A finite element model is set up to evaluate via extrusion during thermal cycling taking into account the actual grain structures near the via top. The elastic anisotropy and plasticity are considered for each Cu grain, and the grain orientation obtained from experimental measurements is directly mapped into the FEA model. GBS is described by a cohesive zone model based on a frictional traction separation relationship. Based on GBS, the via extrusion behavior is deduced for two different Cu/Si interfacial conditions: fully bonded and free sliding, corresponding to the upper and lower bounds of the extrusion. In each case, the effect of GBS is evaluated by analyzing the plasticity and extrusion profiles. The results indicate that GBS plays a dominant role in determining the magnitude and profile of via extrusion.

In this article, the effects of Cu microstructure on the mechanical properties and extrusion of through-silicon vias (TSVs) were studied based on two types of TSVs with different microstructure. A direct correlation was found between the grain size and the mechanical properties of the vias. Both an analytical model and finite element analysis (FEA) were used to establish the relationship between the mechanical properties and via extrusion. The effect of via/Si interface on extrusion was also studied by FEA. The results suggest small and uniform grains in the Cu vias, as well as stronger interfaces between the via and Si led to smaller via extrusion, and are thus preferable for reduced via extrusion failure and improved TSV reliability.

In this work, the effect of grain structure on TSV extrusion and its reliability implication are investigated through experimental measurements and modeling analysis. The grain orientation, elastic anisotropy and local plasticity are found to be important in controlling the extrusion profile which can directly impact the back-end-of-line (BEOL) reliability. Results from this study suggest that the Cu microstructure should be optimized from both global and local aspects in order to minimize the extrusion damage to the 3D structure.

During air-gap formation in interconnects, decomposition process of the sacrificial layer induces deformation of a low-k dielectric cap layer. For analysis of ensuing structural instability, a logistic kinetics model is introduced to describe the removal process of the sacrificial layer, and finite difference method (FDM) is applied to evaluate the deformation behavior of the cap layer. The instability of the cap layer depends on its span length and the degree of adhesion between the cap layer and sacrificial layer. During decomposition, strong adhesion causes the collapse of the cap layer, while the cap deformation remains small and stable with weak adhesion. For intermediate adhesion, a snap-back instability is predicted as the cap layer suddenly detaches from the sacrificial layer at a critical deflection. The critical adhesion energy is predicted as a function of the air gap width.

Copper (Cu) through-silicon via (TSV) is a critical element in three-dimensional (3D) integrated circuits. Typically, fabrication of TSVs involves etching of via holes, deposition of liner and Cu seed layers, electroplating of Cu, post-electroplating annealing, and CMP removal of Cu overburden. In the via-middle scheme widely adopted for 3D integration, the back-end-of-the-line (BEOL) layers are deposited on top of the wafer after the fabrication of TSVs. As one of the reliability issues, extrusion of the Cu vias occurs primarily during the BEOL processing, which can cause the BEOL layers to deform, leading to mechanical and electrical failures of the interconnect structures (Fig. 1) [1-5]. Thus via extrusion has been a major concern for yield and reliability of 3D integration. Previous studies have suggested that the stress and mechanical properties of the Cu via directly affect via extrusion [4-6]. The underlying mechanism of via extrusion has been examined by considering plastic deformation in Cu and via/Si interfacial sliding [7,8]. For the purpose of process optimization, it is important to establish a correlation between the microstructures of the Cu via and the mechanical properties, which in turn can be correlated to via extrusion. In this work, we characterized the microstructures and mechanical properties of Cu TSVs, followed by measurements and modeling of via extrusion.

X-ray microbeam diffraction measurements were conducted for copper (Cu) through-silicon via (TSV) structures. This technique has the unique capability to measure stress and deformation in Cu and in silicon with submicron resolution, which enables direct observation of the local plasticity in Cu and the deformation induced by thermal stresses in TSV structures. Grain growth in Cu vias was found to play an important role in controlling the stress relaxation during thermal cycling and, thus, the residual stress and plasticity in the TSV structure. The implication of the local plasticity on TSV reliability is discussed based on the results from this study and finite element analysis.

In this work, the effect of high temperature storage (HTS) on the stress in and around Cu TSVs in 3D stacked chips is studied by scanning white beam x-ray microdiffraction. The x-ray microdiffraction measurements were conducted on different die levels in the stacked chips before and after HTS test. High resolution mappings of stress distribution were obtained and compared between pre-HTS and post-HTS for both the Cu via and the surrounding Si. The x-ray microdiffraction technique provides a means for nondestructive, direct stress measurement in a 3D die stack structure. Finite element analysis (FEA) was carried out for the test structure to interpret the measurement results and to discuss the thermal aging effect on the 3D chip. Overall, the results show reduced stress in both Cu and Si after HTS, which can be explained by stress relaxation occurred during HTS. The implication of the HTS results on long term reliability of 3D die stacks is discussed.

An analytical approach to predict initiation and growth of interfacial delamination in the through-silicon via structure is developed by combining a cohesive zone model with a shear-lag model. Two critical temperatures are predicted for damage initiation and fracture initiation, respectively. It is found that via extrusion significantly increases beyond the second critical temperature. The dependence of the critical temperatures on the material/interfacial properties, as well as the via size (diameter and height), is discussed. In parallel with the analytical approach, finite-element models with cohesive interface elements are employed to numerically simulate the initiation and the progression of interfacial delamination. The numerical results are in good agreement with the analytical solution, and both are qualitatively consistent with reported experimental findings by others.

Through-silicon via (TSV) is a critical element connecting stacked dies in three-dimensional (3D) integration. The mismatch of thermal expansion coefficients between the Cu via and Si can generate significant stresses in the TSV structure to cause reliability problems. In this study, the thermal stress in the TSV structure was measured by the wafer curvature method and its unique stress characteristics were compared to that of a Cu thin film structure. The thermo-mechanical characteristics of the Cu TSV structure were correlated to microstructure evolution during thermal cycling and the local plasticity in Cu in a triaxial stress state. These findings were confirmed by microstructure analysis of the Cu vias and finite element analysis (FEA) of the stress characteristics. In addition, the local plasticity and deformation in and around individual TSVs were measured by synchrotron x-ray microdiffraction to supplement the wafer curvature measurements. The importance and implication of the local plasticity and residual stress on TSV reliabilities are discussed for TSV extrusion and device keep-out zone (KOZ).

other stress function c(z) can be derived directly by analytic continuation along the traction-free boundary of the unit circle as cðzÞ ¼ À'ð1 z Þ À oð1 z Þ o 0 ðzÞ ' 0 ðzÞ ð28Þ or can be obtained from the Cauchy integral of the conjugate form of (19). References 1. Han J, Norio N (2001) Thermal stress problem for mixed heat conduction boundary around an arbitrarily shaped hole with crack under uniform heat flux. New integral equation for the thermal insulated curve crack problem in an infinite plate. (lnr) singularity at interface cracks in anisotropic bimaterials due to heat flow. stresses of a cracked circular hole due to uniform heat flux. Yobayexiqe 11:381–391 14. Tuji M, Hasebe N (1991) Thermal stresses of crack originating from a corner of a rhombic hole in a plate due to uniform heat flux. Stress intensity factors of cracks initiating from a rhombic hole due to uniform heat flux. Eng Fract Mech 42:331–337 16. Hasebe N, Tomida H, Nakamura T (1989) Solution of displacement boundary value problem under uniform heat flux. A solution of the mixed boundary value problem for an infinite plate with a hole under uniform heat flux. ASME, Thermal stress problem for a partly debonded rigid circular fiber inclusion in an infinite matrix. Solution of an elliptic rigid inclusion with debondings in an infinite plane under the uniform heat flux. J Therm Stress 22:189–212 22. Brock LM (2000) Effects of crack surface convection for rapid crack growth in a thermoelastic solid. Int Overview The thermal stresses in the 3-D packaging originate from the large mismatch in the coefficients of thermal expansion (CTEs) between the materials used in the 3-D structures. Especially, the CTE mismatch between the through-silicon via (TSV), which is an essential component in 3-D packaging, and the Si matrix is the main cause of structural failures in the 3-D packaging. The characteristics of the thermal stress are complex

In this paper, the effects of Cu microstructure on the mechanical properties of TSV and via extrusion are studied using two types of through-silicon vias (TSVs) with different grain size distributions. A direct correlation is found between the Cu grain size and the mechanical properties of the TSVs. An analytical model is used to explore the relationship between the mechanical properties and via extrusion. The results show that small and uniform grains in the Cu vias led to smaller via extrusion. Such grain structures are effective for reducing via extrusion failure to improve TSV reliability.

Continual scaling of devices and on-chip wiring has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, three-dimensional (3-D) integration with through-silicon vias (TSVs) has emerged as an effective solution to meet the future technology requirements. Among others, thermo-mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper presents experimental measurements of the thermal stresses in TSV structures and analyses of interfacial reliability. The micro-Raman measurements were made to characterize the local distribution of the near-surface stresses in Si around TSVs. On the other hand, the precision wafer curvature technique was employed to measure the average stress and deformation in the TSV structures subject to thermal cycling. To understand the elastic and plastic behavior of TSVs, the microstructural evolution of the Cu vias was analyzed using focused ion beam (FIB) and electron backscattering diffraction (EBSD) techniques. Furthermore, the impact of thermal stresses on interfacial reliability of TSV structures was investigated by a shear-lag cohesive zone model that predicts the critical temperatures and critical via diameters.

In this paper, we demonstrated the plasticity mechanism for copper (Cu) extrusion in through-silicon via structures under thermal cycling. The local plasticity was directly observed by synchrotron x-ray micro-diffraction near the top of the via with the amount increasing with the peak temperature. The Cu extrusion was confirmed by Atomic Force Microscopy (AFM) measurements and found to be consistent with the observed Cu plasticity behavior. A simple analytical model elucidated the role of plasticity during thermal cycling, and finite element analyses were carried out to confirm the plasticity mechanism as well as the effect of the via/Si interface. The model predictions were able to account for the via extrusions observed in two types of experiments, with one representing a nearly free sliding interface and the other a strongly bonded interface. Interestingly, the AFM extrusion profiles seemed to contour with the local grain structures near the top of the via, suggesting that the grain structure not only affects the yield strength of the Cu and thus its plasticity but could also be important in controlling the pop-up behavior and the statistics for a large ensemble of vias.

Mechanical robustness of a bonding pad on an electronic device, consisting of the top aluminum layer, 40nm thick intermediate titanium nitride (TiN) barrier layer, and 350nm thick bottom aluminum layer, was investigated with respect to the thickness of top aluminum layer ranging from 250nm to 650nm. Mechanical responses of the pad were evaluated using wire pull test, nanoindentation test, and nanoscratch test. The bonding quality was degraded with the decreasing thickness of top aluminum layer, due to the increasing risk of mechanical damage of this layer and the breakage of the underlying TiN layer. The apparent elastic modulus of the thinner pad increased faster than that of the thicker one as a function of indentation depth. Apparent friction coefficient exhibited a complex, yet understandable, pattern amenable to the relative difficulty of the scratch tip traveling through the three layers in the pad assembly. The breakage of TiN caused an abrupt drop in the load vs. penetration curves in the nanoscratch test, the coincidence of which was verified by subsequent cross-sectional analysis. The longitudinal scratch distance to the TiN breakage can serve as a useful parameter to qualify the mechanical stability of the bonding pad.

Three-dimensional (3-D) integration with through-silicon-vias (TSVs) has emerged as an effective approach to overcome the wiring limit beyond the 32nm technology node. Due to the mismatch of thermal expansion between the via material and Si, thermal stresses ubiquitously exist in the integrated 3-D structures. The thermal stresses can be significant to raise serious reliability issues, such as TSV extrusion and mobility degradation of logic devices. To understand the characteristics of the thermal stresses in TSVs, experimental measurements and numerical analysis are presented in this work. A precision wafer curvature technique was used together with micro-Raman spectroscopy to form a complementary approach to characterize the deformation and stresses in the TSV structures. The microstructures of the Cu vias were analyzed to provide insights to the deformation mechanisms. Guided by the experimental observations, finite element analysis was performed to analyze the thermal stresses taking into account the elastic anisotropy of Si and the plasticity of Cu. It was found that plastic deformation is localized within the Cu vias near the via/Si interface and may play an important role in TSV extrusion. Finally, the effect of thermal stresses on carrier mobility was investigated to evaluate the keep-out zone (KOZ) for logic devices near the TSVs.

The characteristics of thermal stresses in a five-stacked memory dies containing through-silicon vias (TSVs) were measured with synchrotron x-ray microdiffraction. The measurements were performed in and around the Cu vias for both the top and bottom dies. With scanning white beam x-ray microdiffraction, high resolution mappings of stress distribution were obtained. The results provided a direct observation of the local plasticity in Cu TSV and the stress and deformation in the surrounding Si. Thermo-mechanical modeling using finite element analysis (FEA) was carried out for the stacked structure. Results from the modeling analysis were correlated to the synchrotron observation to examine the effect of the die stacking on the stress behavior of the TSV at different die levels. Overall, the stress distribution obtained by FEA showed good agreement with the synchrotron measurement. The presence of plasticity was predicted by FEA and confirmed by the synchrotron observation. The implication of the residual stress on reliability of the memory structure was discussed. The results from this work demonstrate the capability of synchrotron based x-ray technique in studying the stress characteristics of multi-stack TSV structures.

In this study, we investigated the kinetics of intermetallic compound (IMC) growth in Pb-free Sn-based microbumps with Cu or Ni under-bump metallization (UBM) in three-dimension (3D) integration. An analysis was formulated to study the multi-phase multi-component kinetics for solid-state phase transformation of intermetallic growth. A numerical optimization method called simulated annealing (SA) was applied to derive the diffusion coefficients required for the model analysis. The derivation was based on the kinetic data obtained from IMC formation in through-silicon-via (TSV) microbump structures at 170°C. The diffusion coefficients of Cu in Cu3Sn and Cu6Sn5 were found to be 5.12 10-16 m2/s and 9.42 10-16 m2/s, respectively, while those of Sn were found to be 1.46 10-16 m2/s and 9.44 10-16 m2/s in Cu3Sn and Cu6Sn5, respectively. The diffusion coefficients of Ni and Sn in Ni3Sn4 were found to be 1.36 10-17 m2/s and 6.81 10-18 m2/s, respectively. The deduced diffusivities were then applied to a finite difference model to predict the IMC growth kinetics, and the results were verified by the experiments. Finally, the effect of IMC formation on the reliability of microbumps in 3D structures was discussed.

This paper investigated the initial void growth that determines the electromigration failure time for Cu/low-k interconnects. A method to derive the initial void growth rate prior to line failure by analyzing the resistance traces was developed. The statistical data from multi-linked structures show a linear relationship between the void growth rates before and after failure. An extended the Korhonen model was developed taking into account the stress effect on void growth for Cu interconnects. The model was able to account for the observed EM statistics, thus suggesting that the effect of stress should be included for EM lifetime extrapolation.