This paper presents a novel CMOS-compatible negative differential resistance (NDR) device based on SiGe gated diodes. Experimental results on various prototypes show that this device has very high peak currents and the highest reported peak-to-valley current ratios in SiGe systems to date. This NDR element can be easily integrated into a normal 1T1C DRAM cell to enable an SRAM-like operation with a much more compact cell size

As the size of metal oxide semiconductor devices continues to be scaled down to sub-90 nm, novel materials must be integrated successfully in order to meet the technical demands. Nickel silicide (NiSi) is being considered as an alternative material to cobalt silicide (CoSi2) for the self-aligned silicide process, because it forms at lower temperatures with less silicon consumption and is compatible with SiGe. In order to prevent excessive silicidation in narrow gate lines and at the edges of source/drain regions, NiSi integration requires limiting silicidation kinetics via reduced thermal budgets followed by forming the low resistance phase. This paper focuses on the low temperature regime of the Ni-Si reaction through the use of soak RTP at 300 degrees C and spike RTP at 300 similar to 400 degrees C. In order to study the formation of Ni2Si and NiSi and the transformation from Ni2Si to NiSi, the silicide films are characterized by Rs sheet resistance measurements, XRD for phase identification, and TEM for microstructure. The intermediate phase of Ni2Si is formed at 270 degrees C and its growth is observed with increasing anneal time. At temperatures above 300 degrees C, the NiSi phase is found in addition to the Ni2Si phase, and the transformation from Ni2Si to NiSi is observed. The sequence of the Ni2Si-NiSi transformation involves the initial formation of NiSi and the change in the alignment of the crystal planes as the low resistance phase of NiSi forms. Two RTP schemes, soak RTP and spike RTP, follow parallel trends in the sequence of the Ni2Si-NiSi transformation with marked differences in the reaction kinetics.

This paper explores stress management in SiGe with two kinds of structures, namely, epitaxial SiGe films on small pillars and fins. In addition to the compliant substrate effect in the film/fin structures, the geometric effect in the film/pillar structures plays another important role in critical thickness enhancement. The stress-strain states of these two systems are calculated and the equilibrium critical thicknesses are predicted, using the work method, for different fin thicknesses, pillar radii, and Ge concentrations. Compared to conventional films grown on planar bulk substrates, the critical thicknesses for fin and pillar structures are increased significantly. SiGe films with various thicknesses and compositions were epitaxially grown around vertical fins and horizontal membranes with thicknesses as thin as 12nm to demonstrate the concepts. Cross-sectional transmission electron microscopy analysis showed that dislocation densities are much smaller than for films grown on bulk Si substrates. The dislocation density versus fin thickness also illustrated the expected trend.

In NOR flash memories, there is a strong desire to scale the drain programming voltage and operating power for use in portable applications. Low power consumption in these memories can be achieved by increasing their injection efficiency (IE) (=I/sub G//I/sub D/), either by using novel device structures or programming mechanisms. Device structures based on the band-to-band hot electron (BBHE) concept have traditionally shown the highest IE but the IE drops dramatically at low drain voltages. In this letter, we analyze the reasons for this reduction in IE at low V/sub DS/ and propose new silicon-on-insulator (SOI)-based cells that circumvent the above limitation. Experimental structures fabricated show extremely high IE (10/sup -3/), up to 5-10 times higher than conventional BBHE cells at very low gate and drain voltages.

Part I of this paper dealt with the fundamental understanding of device physics and circuit design in a novel transistor, based on the field-effect control of impact-ionization (I-MOS). This paper focuses on experimental results obtained on various silicon-based prototypes of the I-MOS. The fabricated p-channel I-MOS devices showed extremely abrupt transitions from the OFF state to the ON state with a subthreshold slope of less than 10 mV/dec at 300 K. These first experimental prototypes of the I-MOS also showed significant hot carrier effects resulting in threshold voltage shifts and degradation of subthreshold slope with repeated measurements. Hot carrier damage was seen to be much worse in nMOS devices than in pMOS devices. Monte Carlo simulations revealed that the hot carrier damage was caused by holes (electrons) underneath the gate in pMOS (nMOS) devices and, thus, consequently explained the difference in hot carrier effects in p-channel versus n-channel I-MOS transistors. Recessed channel devices were also explored to understand the effects of surfaces on the enhancement in the breakdown voltage in I-MOS devices. In order to reduce the breakdown voltage needed for device operation, simple p-i-n devices were fabricated in germanium. These devices showed much lower values of breakdown voltage and excellent matches to MEDICI simulations.

Ge on insulator (GOI) is desired to obtain metal-oxide-semiconductor transistors with high performance and low leakage current. We have developed a method to make GOI based on liquid-phase epitaxial (LPE) growth on Si substrates and a defect necking technique in which defects are confined to a very short distance. Self-aligned microcrucibles were used to hold the Ge liquid. High-quality single-crystal (100) as well as (111) oriented GOI structures were obtained with a process compatible with Si-based fabrication. No dislocations or stacking faults were found in the LPE Ge films on insulator. The orientation of the Ge crystals was controlled by the seeding Si substrate. This method opens up the possibility of integrating Ge device structures in a baseline Si integrated circuit process.

We have developed a novel rapid melt growth technique to produce Ge-on-insulator (GeOI) substrates with very high quality. P-channel MOSFETs, tri-gate MOS transistors and p-i-n photodetectors were fabricated with these GeOI structures. The entire process flow for these devices is fully compatible with base-line Si CMOS fabrication. The high E/sub Eff/ hole mobility of the pMOSFETs was estimated to be 120cm/sup 2//Vs, comparable to the reported results with bulk Ge wafers. The fabricated photodetectors showed high responsivity and very fast impulse response.

Ion implantation followed by laser annealing has been used to create supersaturated and electrically active concentrations of antimony in silicon. Upon subsequent thermal annealing, however, these metastable dopants deactivate towards the equilibrium solubility limit. In this work, the formation of inactive antimony structures has been studied with grazing incidence diffuse x-ray scattering, and transmission electron microscopy, and the results are correlated to previous high-resolution x-ray diffraction data. We find that at a concentration of 6.0×1020 cm−3, small, incoherent clusters of radius 3–4 Å form during annealing at 900 °C. At a higher concentration of 2.2×1021 cm−3, deactivation at 600 °C occurs through the formation of small, antimony aggregates and antimony precipitates. The size of these precipitates from diffuse x-ray scattering is roughly 15 Å in radius for anneal times from 15 to 180 seconds. This value is consistent with the features observed in high-resolution and mass contrast transmission electron microscopy images. The coherent nature of the aggregates and precipitates causes the expansion of the surrounding silicon matrix as the deactivation progresses. In addition, the sensitivity of the diffuse x-ray scattering technique has allowed us to detect the presence of small clusters of radius ∼2 Å in unprocessed Czochralski silicon wafers. These defects are not observed in floating zone silicon wafers, and are tentatively attributed to thermal donors.

As the size of metal-oxide-semiconductor (MOS) devices continues to be scaled aggressively, new technologies must be developed in order to meet future device requirements. One area that faces serious challenges involves reducing the parasitic series resistances between the channel and the contact. In this work, we demonstrate that laser annealing is a potential alternative annealing technique to form ultra-shallow, low resistivity junctions. This method benefits from the ability to create abrupt, uniform dopant profiles with active concentrations that can exceed the equilibrium solubility limits. We also address some of the issues preventing its adaptation into the semiconductor-processing scheme, including the annealing of patterned structures, dopant deactivation and junction depth control.

As semiconductor device dimensions continue to decrease, the main challenge in the area of junction formation involves decreasing the junction depth while simultaneously decreasing the sheet resistance. Laser annealing is being investigated as an alternative to rapid thermal annealing to repair the damage from ion implantation and to activate the dopants. With this technique, uniform, box-shaped profiles are obtained, with dopant concentrations that can exceed equilibrium solubility limits at normal processing temperatures. Unfortunately, these super-saturated dopant concentrations exist in a metastable state and deactivate upon further thermal processing. In this article, we describe a comprehensive study of the deactivation kinetics of common dopants (P, B, and Sb) across a range of concentrations and annealing conditions. For comparison, As deactivation data from the literature is also presented. P and As deactivate substantially at temperatures as low as 500 °C, while Sb at moderate concentrations and B remain fully active until 700 to 800 °C. It is proposed that As and P deactivate through the formation of small dopant-defect clusters while B deactivates through precipitation. The proximity to the surface is shown to be a second-order effect.

We theoretically investigate the relationship between impurity diffusion profiles and the underlying atomic-scale diffusion mechanisms that occur via intermediate species in elemental semiconductors. We focus particularlyon diffusion regimes characterized by short versus long diffusion times and low versus high transport capacities. Based on analytic derivations and numerical simulations, we show that, in the absence of any external point defect perturbation, there is usually no unique correspondence between a microscopic diffusion mechanism and a macroscopic impurity diffusion profile. Complementary experiments have to be performed to gain more conclusive information about the microscopic diffusion mechanisms. Examples of these experiments are perturbing the point defect concentrations from equilibrium by thermal oxidation and nitridation, particularly in the short-time diffusion regime, and studying the growth or shrinkage of stacking faults and dislocation loops. Finally, a wide range of impurity diffusion phenomena result from the presence of intermediate species, and can be analytically derived or numerically computed starting from the same set of diffusion equations.

Ultra-low energy implants were used in combination with rapid thermal anneals in the temperature range 900 degreesC-1050 degreesC to study dopant activation in silicon. First, relatively long time anneals were performed in a conventional tungsten-based RTA to investigate the activation mechanisms. The activation was monitored using Hall measurement, where the rate of electrical activation was considered by measuring the time it takes to reach 50% activation. Using Arrhenius fits, an activation energy was extracted, and it was found that while boron has a mean activation energy for electrical activation of 4.7 eV in agreement with previous studies, arsenic and phosphorus have thermal activation energies of 3.6 eV and 4.1 eV, respectively. The 4.7 eV activation energy for boron is believed to be related to a point defect driven mechanism for electrical activation. Electrical activation of arsenic and phosphorus, however, seems to be related to dopant diffusion. In the second set of experiments, an arc lamp system was utilized to perform ultra-sharp spike anneals and to analyze the effect of both ramp-up and ramp-down on boron and arsenic activation and diffusion. For both dopants, it was found that for a given temperature, there is an optimum ramp-rate that produces the desired dopant activation and junction depth.

The kinetics of boron electrical activation is studied for both pre-amorphized (PAI) and non-amorphized (non-PAI) samples. It is found that the electrical activation mechanism in both cases is similar and is dominated by a 5eV native point defect driven activation energy barrier, substantially greater than the 3.5eV diffusion activation energy. The physical origins of this mechanism are explained through atomistic simulations and the physical basis of the activation energy difference was used to design a flash anneal capable of achieving highly active and ultra shallow p-type junctions meeting the 32nm node ITRS specifications.

This paper presents a detailed study of the impact of lateral doping abruptness in the source/drain extension region and the gate-extension overlap length on device performance. Proper choice of the metric used to compare the different device designs is essential. Series resistance and threshold voltage roll-offs are shown to be incomplete measures of device performance that could lead to inconsistent lateral abruptness requirements. While series resistance is seen to improve with increasing junction abruptness, threshold voltage roll-off could be degraded by both lateral junctions that are too gradual and too abrupt-in contrast to the conventional scaling assumptions. The I-on(supernominal)-I-off(subnominal) plot, which takes into account statistical variations of gate length, is proposed as a good metric for comparing different device technology designs. Gate-extension overlap length is shown to interact with lateral doping abruptness and to have a significant impact on device performance.

The role of fluorine in suppressing boron diffusion was investigated by utilizing a buried dopant marker to monitor the interaction of fluorine with interstitials. A boron spike with a peak concentration of 1.2×1018 cm−3 followed by 500 nm of undoped silicon was grown in a low pressure chemical vapor deposition furnace. The wafers were then preamorphized and implanted with either B, B and F, BF2, As, As and F, or F, respectively. Following the implants, the samples were rapid thermal annealed (RTA) at 1050 °C for very short times (spike). The use of preamorphization allows the chemical effect of fluorine to be analyzed independently of implant damage, and the buried layer functions as an indicator of point defect (in this case Si self-interstitial) perturbation. As expected, secondary ion mass spectroscopy shows that the presence of fluorine retards the diffusion of boron. In addition, the retained fluorine dose after the RTA is highest in the boron-implanted samples. In all samples the buried layer has diffused by the same amount, indicating that there is no change to the silicon self-interstitial population due to fluorine. These results suggest that fluorine has a chemical effect, and retards boron diffusion by mainly bonding with boron.

Laser annealing is being investigated as an alternative method to activate dopants and repair the lattice damage from ion implantation. The unique properties of the laser annealing process allow for active dopant concentrations that exceed equilibrium solubility limits. However, these super-saturated dopant concentrations exist in a metastable state and deactivate upon subsequent thermal processing. Previously, this group compared the electrical characteristics of the deactivation behavior of common dopants (P, B, and Sb) across a range of concentrations and annealing conditions. Boron and antimony were shown to be stable species against deactivation while P and As deactivate quickly at temperatures as low as 500 °C. In this work, we present additional data to understand the underlying physical mechanisms involved in the deactivation process. It is proposed that As and P deactivate through the formation of small dopant—defect clusters while B and Sb deactivate through precipitation.

We present a technology and its mechanism to obtain single-crystalline Si pillars on SiO2 using a two-step Ni-induced crystallization process on amorphous Si pillars with confined sizes. The amorphous Si pillars with a Ni cap were first annealed at 400 °C for 15 h so that a single-crystalline NiSi2 template was formed on top of each pillar. In the second step, they were annealed at 550 °C for 2 h, during which single-crystalline Si pillars were formed by NiSi2-mediated solid-phase epitaxy. These single-crystalline Si pillars can be used for advanced vertical metal–oxide–semiconductor transistors and surround-gate structures, especially where low-temperature processing is required.

The use of silicon germanium (SiGe) heterostructures in vertical surrounding-gate MOSFETs provides an additional means for tailoring current-voltage (I-V) characteristics by controlling physical effects inside the device. Incorporation of an SiGe layer in the vertical MOSFET source can delay the floating-body effect by changing the back injection efficiency and current gain of the parasitic bipolar junction transistor (BJT). Structures with abrupt and ramped SiGe source layers showed up to 2 V and 6 V increases in breakdown voltage at low gate voltages with suppression of the floating-body effect kink. Comparison of simulation to experiment displayed the difficulties of accurately predicting device parameters, but demonstrated the usefulness of simulation to qualitatively predict device behavior.

The integrated circuit (IC) industry has followed a steady path of shrinking device geometries for more than 30 years. It is widely believed that this process will continue for at least another ten years. However there are increasingly difficult materials and technology problems to be solved over the next decade if this is to actually occur, and beyond ten years there is great uncertainty about the ability to continue scaling metal-oxide-semiconductor field-effect transistor (MOSFET) structures. This paper describes some of the the most challenging materials and process issues to be faced in the future and where possible solutions are known, describes these potential solutions. The paper is written with the underlying assumption that the basic metal-oxide-semiconductor (MOS) transistor will remain the dominant switching device used in ICs and it further assumes that silicon will remain the dominant substrate material.

The use of silicon germanium (SiGe) heterostructures in vertical surrounding gate MOSFETs provides an additional means for tailoring current-voltage (I-V) characteristics by controlling physical effects inside the device. Incorporation of an SiGe layer in the vertical MOSFET drain can modify hot-carrier characteristics via material dependent impact ionization coefficients. MOSFETs with ramped SiGe drain layers showed increased drain current in the soft breakdown regime, due to increased impact ionization as verified by substrate current measurement, with up to 1.5 V decreases in breakdown voltage. Comparison of simulation to experiment displayed the difficulties of accurately predicting device parameters, but demonstrated the usefulness of simulation to qualitatively predict device behavior without costly expenditures of time, material, and equipment.