We present the process development and device characterization of the Selectively Compensated Collector (SCC) BJT specifically designed for high-density deep-submicrometer BiCMOS SRAM technologies. This double-poly BJT takes advantage of the self-aligned polysilicon layers of the SRAM bit cell to obtain high performance without adding excessive process complexity, Furthermore, although an NPN de,ice, the SCC BJT is formed in a lightly doped p-well in which the collector is formed with a single 370 keV phosphorus implant to minimize parasitic junction capacitances without the use of trench isolation or recessed oxides, The suitability of this bipolar structure outside of its original FSRAM intent is proven with its potential for bipolar logic and mired-mode RF applications, ECL delays of 50 ps at 200 mu A and a CML poser-delay product of 4.5 fJ at 1.1 V supply were obtained, A 900 MHz noise figure as low as 0.54 dB at 0.5 mA with an associated gain of 14.7 dB was demonstrated as well as a dual modulus divided by 4/5 prescaler operating up to 3.3 GHz for a switch current of 200 mu A.

We present the performance improvements obtained both by scaling the Selectively Compensated Collector (SCC) BJT and by using a modified Current-Mode Logic (CML) gate configuration. Scaling the perimeter parasitics by using the (tighter) bitcell design rules results in a approximately 30% reduction in parasitic capacitances, and a 23% lower power-delay product; reducing it from 48 fJ to 37 fJ. The greatest return comes from using a modified CML gate, which has an n-MOS current source. At a supply voltage of 1.1 V, and at 40 muA switching current, the minimum power-delay product of this CML gate is a silicon-substrate bipolar record 4.5 fJ.

An advanced, high-performance, quadruple well, quadruple polysilicon BICMOS technology has been developed for fast 16 Mb SRAM's. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 mu m(2) with conventional I-line lithographpy and 7.32 mu m(2) with I-line plus phase-shift or with deep UV lithography, The process features PELOX isolation to provide a 1.0 mu m active pitch, MOSFET transistors designed for a 0.80 mu m gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability, A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance.

This paper presented the bipolar RF and circuit characterization of a high-performance 0.35 /spl mu/m BICMOS technology specifically designed for fast SRAMs. A 900 MHz noise figure as low as 0.54 dB at 0.5 mA, prescaler operation up to 3.3 GHz for a switch current of 200 pA, and unstacked CML operation down to 1.0 V yielding a 4.8 fJ power-delay product were reported.<>

A theoretical study of the device characteristics of the Ge/sub x/Si/sub 1-x//silicon inversion-base transistor (BICFET) is presented. This transistor uses the space charge of holes in a modulation-doped inversion channel to control vertical electron transport. This study is of interest not only because of the unique interaction of transport mechanisms in the BICFET but also because the BICFET is ...

An advanced, high-performance BiCMOS technology has been developed for fast 16Mb SRAMs. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 mu m/sup 2/ with conventional i-line lithography and 7.32 mu m/sup 2/ with i-line phase-shift lithography. The process features PELOX isolation to provide a 1.0 mu m active pitch, MOSFET transistors designed for a 0.80 mu m gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance,.<>

This paper describes the fabrication, material characterization, and electrical evaluation of the p-channel GexSi1-x/Silicon Inversion-Base Transistor (BICFET). The BICFET was one of the first bipolar devices to take advantage of the breakthroughs in advanced GexSi1-x/Si processing technology, to which its p-channel implementation is ideally suited [1], [2]. At this time, the performance limitations of the GexSi1-x/Si BICFET are set only by the current fabrication technology, and not by limits imposed by its physical principles of operation. The electrical results presented here include both the unipolar characteristics, in which the BICFET is configured as a heterojunction FET, and the bipolar characteristics, which is the intended high-performance mode of operation. A companion paper [3] describes in detail the device behavior and theoretical models of the GexSi1-x/Si BICFET. The experimental results presented here are in good agreement with this theoretical study.

This paper describes a novel bipolar technology which achieves very high ECL performance while maintaining low process complexity, large fabrication tolerances, and full CMOS compatibility. The high NPN BJT performance is achieved by using a p-type collector well rather than a conventional n-well. This allows a large decrease in the junction capacitances of the BJT. Furthermore, the BJT can be merged in the same well as the diffused ECL load resistor, resulting in a substantial area savings and further performance improvement. A minimum power-delay product of 50 fJ for a standard ECL gate is demonstrated for these devices.<>

The fabrication, material characterization, and electrical evaluation of the p-channel Ge/sub x/Si/sub 1-x//silicon inversion-base transistor (BICFET) are described. The BICFET was one of the first bipolar devices to take advantage of the breakthroughs in advanced Ge/sub x/Si/sub 1-x//Si processing technology, to which its p-channel implementation is ideally suited. At this time, the performance l...

A novel dc method for determining the components of series resistance in bipolar transistors is presented. As a dc technique, it shows unprecedented accuracy as demonstrated by its application to both metal-contacted heterojunction transistors and more conventional bipolar junction transistors (BJT's). The measurement error was minimized by using a single double-base Kelvin-tapped transistor to extract all components of series resistance. This extraction technique was applied to transistors from an industrial poly-contacted BJT process with various geometries. This paper describes the theory and application of this new extraction technique in both its simplified form, where the emitter resistance is assumed to be lumped and bias-independent, and in its more general form, where it includes the distributed nature of both the emitter and the intrinsic base resistances. This work indicates that past methods for calculating the bias dependence of series resistances in bipolar devices are incorrect. An exact expression for the dc and ac bias-dependent intrinsic base resistance and a methodology for calculating effective resistance for bipolar devices will therefore also be presented.

The authors demonstrate that the optimal 2-D collector doping profile for BiCMOS technologies is a strong function of the intended circuit application of the BJT (bipolar junction transistor). The 2-D collector doping profile in this study was tailored by selectively implanting the collector (SIC) into only the intrinsic region of the BJT. A controlled comparison between SIC and conventional collector implant devices was made by keeping BV/sub CEO/ and beta invariant. It is concluded that selectively implanting the collector into the intrinsic area is advantageous for low-current, but detrimental for high-current gates.<>

A novel DC method for determining the components of series resistance in bipolar transistors is presented. As a DC technique, it shows unprecedented accuracy as demonstrated by its application to both metal-contacted heterojunction transistors and more conventional bipolar junction transistors. The measurement error was minimized by using a single double-base Kelvin-tapped transistor to extract all components of series resistance. The present work indicates that past methods for calculating the bias dependence of series resistances in bipolar devices are incorrect. Therefore, a correct expression for the bias-dependent intrinsic base resistance is also presented.<>

The DC characteristics of advanced heterojunction Ge/sub x/Si/sub 1-x/-Si inversion base transistors are presented. Current gains as high as 1720 with a zero bias pinch resistance of R/sub B/=43 k Omega / Square Operator were obtained. This is believed to be the largest room-temperature current gain reported for any Ge/sub x/Si/sub 1-x/ bipolar device to date. In addition, the effects of varying the germanium concentration on both the Gummel plots and current gain versus temperature were explicitly shown. Due to the technological difficulty in obtaining sharp boron doping profiles in this type of bipolar structure, the vertical performance of these Ge/sub x/Si/sub 1-x/ bipolar devices was significantly improved by maximizing the amount of boron dopant in the Ge/sub x/Si/sub 1-x/ base layer.<>

Operational bipolar inversion-channel field-effect transistors (BICFETs) based on the Ge/sub x/Si/sub 1-x//Si system are discussed. The 300 K current gain of beta =365 at a current density of J/sub c/=2.5*10/sup 4/ A/cm/sup 2/ is the highest value reported for any BICFET to date. The use of a double-heterojunction inversion channel eliminates the collector offset voltage. The present devices are limited by the channel resistance, so that performance improvements are expected for laterally-scaled-down devices.<>

The first operational BICFET (bipolar-inversion-channel field-effect transistor) structures based on the Ge/sub x/Si/sub 1-x//Si system have been demonstrated. The 300 K current gains of beta >300 are believed to be the highest values reported for a BICFET in any material system to date. The device structure, fabrication, and electrical performance are presented. It is concluded that due to its small vertical dimensions and ability to scale laterally, this device shows promise for both discrete and VLSI high-speed applications.<>