Transformer models have achieved remarkable contextual comprehension capabilities in recent years, mainly thanks to the self-attention mechanism. As the input sentence becomes longer, the computation of the attention quadratically increases and becomes the bottleneck. The dynamic sparsity is a prevalent approach to alleviate this problem. However, existing sparse attention accelerators incur substantial redundant computations, reaching the performance limitation. They typically employ single-level sparse structure, supporting multiple or fine-grained N:M sparse patterns, which fails to accommodate the diverse sparse pattern with low hardware overhead. By re-examining the distribution of sparsity patterns, we observe that more high-level sparsity exists across multi-level and within each level with negligible hardware overhead. With multi-levels, more hierarchical sparsity patterns can be exploited without increasing the tile size. Within each level, we further prune redundant elements in an NM-aware manner that fits sparsity patterns dynamically with global information. Motivated by the observation, this paper proposes AMS, an efficient Attention accelerator with Dynamic Multi-level Structured Sparsity. AMS exploits structured sparsity patterns using dynamic multi-level structure in a small tile size, resulting in both high sparsity and low hardware overhead. These structured patterns enable a coordinated optimization of both scheduling and compute array. Compared to DynaX, SOFA, Highlight, STA, and RTSA, AMS achieves speedups of 1.7×, 2.6×, 3.8×, 2.3×, and 16.1×, with power-efficiency gains of 1.6×, 2.4×, and 6.3× over DynaX, SOFA, and Highlight. Compared to V100, A100, and DFSS, AMS achieves speedups of 6.7×, 2.1×, and 1.3×, and power-efficiency gains of 35.2×, 18.1×, and 11.3×.

Coarse-grained reconfigurable arrays (CGRAs) have become prevailing to accelerate regular kernels coupled with a host processor. As the end-to-end applications are increasingly complex, it is necessary to consider mapping whole programs onto a monolithic CGRA, to avoid the bottleneck of host communication implied by Amdahl's law. State-of-the-art studies have developed compiling methods that spatially pipeline the whole program over hardware with many cores. However, these methods mainly focus on static reconfigurable dataflow architectures (RDAs) and fail to exploit the dynamic reconfiguration potential of dataflow architectures, resulting in suboptimal performance and underutilization of hardware resources. Nevertheless, it is nontrivial to generate a performant mapping on dynamic RDAs since instruction-level deadlocks are introduced. To address this challenge, this article proposes EDWAC, a whole-program compiler that generates high-quality configurations for dynamic RDAs. EDWAC resolves the deadlock problem by a two-stage deadlock-prevention mechanism, which comprises a shared-resource-constrained Place and Route (PnR) stage, and a finite state machine (FSM)-based resource reallocation stage. Together with a gated control flow intermediate representation (IR) design and throughput-oriented optimization methods, EDWAC achieves exceptional resource utilization and PnR feasibility.

We present SharpSAT, a heuristic-learning SAT accelerator that achieves fast solution times of 0.8 mu s for SAT and 16.1 mu s for UNSAT cases. Our design integrates: a fast clause learning unit that prunes the search space by deriving constraints from conflicts; a dual-BCP unit that accelerates implication propagation; and a heuristic variable decider introducing non-determinism to efficiently traverse the solution space. A 28nm prototype demonstrates 21.11x/2.61x (SAT/UNSAT) speedup over prior accelerators.

Dataflow-based coarse-grained reconfigurable architectures (CGRAs) and dynamic high-level synthesis (DHLS) are both promising for accelerating applications with nontrivial control and memory behavior, but existing compilation flows are typically fragmented and often struggle with control handling, memory ordering, and effective resource reuse. In particular, prior CGRA compilers are still limited in compiling control-rich programs, while existing DHLS flows are not well aligned with dataflow CGRA compilation. This paper presents RedPanda, a unified compilation frame work for both dataflow-based CGRAs and DHLS. The main contribution of RedPanda is a shared front- and middle-end built on a common RedPanda IR, which enables the two targets to reuse the same core compiler infrastructure. On top of this foundation, RedPanda introduces static analyses and transformations for branch handling, memory ordering, aggressive loop pipelining, and time-multiplexing-aware compilation, thereby improving support for control-/memory-irregular workloads while reducing unnecessary serialization and instruction overhead. After this shared compilation stage, the IR is lowered to target-specific back-end flows for CGRA mapping and DHLS circuit generation. Experimental results show that RedPanda reduces CGRA spatial execution cycles by 33.4%, improves temporal-CGRA resource efficiency by 37%, and reduces instruction count by about 13%. For HLS, RedPanda achieves at least 34% faster execution while using fewer LUT, DSP, and FF resources. These results demonstrate that RedPanda provides a practical unified compilation foundation for both CGRA and DHLS targets.

Boolean satisfiability (SAT) is a fundamental problem in formal verification and symbolic reasoning. In correctness-critical domains such as hardware verification and safety-critical systems, complete SAT solving is required to provide formal unsatisfiability guarantees. Boolean constraint propagation (BCP) dominates execution time in modern complete SAT solvers and is the primary performance bottleneck. This bottleneck arises because BCP is memory-bound and requires aggregating the states of many literals during clause evaluation. Such aggregation-centric access patterns incur substantial overhead in conventional digital implementations, while existing hardware accelerators either sacrifice solver completeness for throughput or preserve correctness with high logic and interconnect costs. To address these limitations, we propose HiPACS, a hierarchical mixed-signal in-memory architecture that accelerates BCP through analog charge-domain aggregation. HiPACS performs clause evaluation directly in memory, reducing data movement and digital reduction overhead. A hierarchical organization enables efficient and low-latency propagation using lightweight, low-resolution analog interfaces. To preserve solver completeness and correctness, HiPACS integrates a near-memory digital controller for decision making, backtracking, and conflict analysis, supporting both Davis–Putnam–Logemann–Loveland (DPLL) and Conflict-Driven Clause Learning (CDCL). On standard benchmarks, HiPACS achieves up to 665× speedup over Kissat on satisfiable instances and up to 8.6× over prior complete SAT accelerators, demonstrating the effectiveness and practicality of mixed-signal in-memory BCP for complete SAT acceleration.

CPU simulators are vital for computer architecture research, primarily for estimating performance under different programs. This poses challenges for fast and accurate simulation of modern CPUs, especially in multi-core systems. Modern CPU peformance simulators such as GEM5 adopt the cycle-accurate and event-driven approach, which is timeconsuming to simulate the extensive microarchitectural behavior of a real benchmark running on out-of-order CPUs. Recently, machine leaning based approach has been proposed to improve simulation speed, but they are currently limited to estimating the cycles of basic blocks rather than the complete benchmark program. This paper introduces a novel ML-based CPU simulator named CAPSim, which uses an attention-based neural network performance predictor and instruction trace sampling method annotated with context. The attention mechanism effectively captures long-range influence within the instruction trace, emphasizing critical context information. This allows the model to improve performance prediction accuracy by focusing on important code instruction. CAPSim can predict the execution time of unseen benchmarks at a significantly fast speed compared with an accurate O3 simulator built with gem5. Our evaluation on a commercial Intel Xeon CPU demonstrates that CAPSim achieves a 2.2 - 8.3x speedup compared to using gem5 built simulator, which is superior to the cutting-edge deep learning approach

Boolean satisfiability (SAT), the first proven non-deterministic polynominal-complete problem, is crucial in dataintensive applications. Different applications have a wide spectrum of SAT problem sets (scale, complexity) and also various solution requirements (algorithm completeness, speed). Current SAT solvers are insufficient for providing ideal solutions under different scenarios. This work presents the Chameleon-SAT, the first ASIC-based SAT accelerator that can support local search, Davis-Putnam- Logemann-Lovel, Conflict-Driven Clause Learning algorithms, while leveraging the efficient mixed-signal inmemory computing architecture to achieve orders-of-magnitude improvements in speed compared to the prior SAT solvers. By judiciously selecting the reconfiguration mode, Chameleon-SAT is able to solve a wide range of the SAT problems to achieve smallscale, high-complexity cases (>= 90x for 20 variables/ 86 clauses, satisfiable problems), medium-scale, structured cases (>= 19x for 50 variables/ 215 clauses, unsatisfiable problems), and largescale, high-complexity cases (>= 7x for 100 variables/ 430 clauses, satisfiable problems).

DIMM-based Near-Memory-Processing (NMP) kernel offloading enables a program to execute in computation-enabled DIMM buffer chips, bypassing the bandwidth-constrained CPU main memory bus for high performance. Yet, it also enables programs to access memory without restrictions and protection from CPU, resulting in potential security hazards. To protect general NMP kernel offloading even with malicious privileged software, a heterogeneous TEE is required. However, for architectural design simplification, the conventional heterogeneous TEE design isolates host CPU process from NMP kernel's memory and vice versa, such that CPU TEE and trusted NMP driver can protect CPU processes and NMP kernels in complete separation. Such isolation results in redundant input/output data movement between the two isolated memory spaces, with half of the movement performed by host CPU. Worsened by limited CPU memory bandwidth, we identify that such redundancy severely bottlenecks the performance of many potential NMP applications. To overcome this bottleneck, we propose to abandon isolation and share the NMP kernel memory with its host CPU process. Based on this idea, we design SSS-DIMM, an efficient TEE for DIMM-based NMP kernel offloading that removes the redundant data movement via Secure Space Sharing. SSS-DIMM resolves the two security challenges faced by memory sharing: to provide consistent security guarantees on CPU processes and NMP kernels with CPU TEE and the NMP driver for both memory ownership (allocation) and views (mapping), and to ensure that cryptography metadata be securely shared and synchronized between CPU and NMP unit. Our evaluation shows that SSS-DIMM maintains both security and high performance.

Fully Homomorphic Encryption (FHE) is a set of powerful cryptographic schemes that allows computation to be performed directly on encrypted data with an unlimited depth. Despite FHE's promising in privacy-preserving computing, yet in most FHE schemes, ciphertext generally blows up thousands of times compared to the original message, and the massive amount of data load from off-chip memory for bootstrapping and privacy-preserving machine learning applications (such as HELR, ResNet-20), both degrade the performance of FHE-based computation. Several hardware designs have been proposed to address this issue, however, most of them require enormous resources and power. An acceleration platform with easy programmability, high efficiency, and low overhead is a prerequisite for practical application. This paper proposes EFFACT, a highly efficient full-stack FHE acceleration platform with a compiler that provides comprehensive optimizations and vector-friendly hardware. We start by examining the computational overhead across different real-world benchmarks to highlight the potential benefits of reallocating computing resources for efficiency enhancement. Then we make a design space exploration to find an optimal SRAM size with high utilization and low cost. On the other hand, EFFACT features a novel optimization named streaming memory access which is proposed to enable high throughput with limited SRAMs. Regarding the software-side optimization, we also propose a circuit-level function unit reuse scheme, to substantially reduce the computing resources without performance degradation. Moreover, we design novel NTT and automorphism units that are suitable for a cost-sensitive and highly efficient architecture, leading to low area. For generality, EFFACT is also equipped with an ISA and a compiler backend that can support several FHE schemes like CKKS, BGV, and BFV.

Point cloud analytics plays a crucial role in spatial machine vision for applications like autonomous driving, robotics and AR/VR. Recently, numerous domain-specific accelerators have been proposed to meet the stringent real-time and energy-efficiency demands of embedded and mobile platforms. However, most existing point cloud accelerators are kernel-independent hardware architectures, which face significant limitations and struggle to adapt to the rapidly evolving nature of point cloud applications. To address these challenges, we propose PointISA, a novel Instruction Set Architecture (ISA) extension designed for efficient point cloud analytics through architecture and algorithm co-design. First, we incorporate specialized instructions into PointISA for point cloud processing, such as Euclidean distance computation and multidimensional sorting. And then, we present an unified hardware architecture that efficiently executes both PointISA's specialized instructions and conventional matrix multiplication. Finally, we optimize key algorithms like farthest point sampling and k-nearest neighbors, adapting them into parallel multiple-points-to-multiplepoints (MP2MP) patterns that fully exploit the architecture's parallel capabilities while maintaining algorithmic correctness. Evaluation shows that PointISA achieves an average 5.4x speedup and 4.9x improvement in power efficiency across diverse point cloud workloads while incurring a negligible area overhead of 0.9%.

The Transformer architecture has achieved tremendous success in natural language processing, computer vision, and scientific computing through its self-attention mechanism. However, its core components-positional encoding and attention mechanisms-have lacked a unified physical or mathematical interpretation. This paper proposes a structural theoretical framework that integrates positional encoding, kernel integral operators, and attention mechanisms for in-depth theoretical investigation. We map discrete positions (such as text token indices and image pixel coordinates) to spatial functions on continuous manifolds, enabling a field-theoretic interpretation of Transformer layers as kernel-modulated operators acting over embedded manifolds.

This paper presents a gate-level Boolean evolutionary geometric attention neural network that models images as Boolean fields governed by logic gates. Each pixel is a Boolean variable (0 or 1) embedded on a two-dimensional geometric manifold (for example, a discrete toroidal lattice), which defines adjacency and information propagation among pixels. The network updates image states through a Boolean reaction-diffusion mechanism: pixels receive Boolean diffusion from neighboring pixels (diffusion process) and perform local logic updates via trainable gate-level logic kernels (reaction process), forming a reaction-diffusion logic network. A Boolean self-attention mechanism is introduced, using XNOR-based Boolean Query-Key (Q-K) attention to modulate neighborhood diffusion pathways and realize logic attention. We also propose Boolean Rotary Position Embedding (RoPE), which encodes relative distances by parity-bit flipping to simulate Boolean “phase” offsets. The overall structure resembles a Transformer but operates entirely in the Boolean domain. Trainable parameters include Q-K pattern bits and gate-level kernel configurations. Because outputs are discrete, continuous relaxation methods (such as sigmoid approximation or soft-logic operators) ensure differentiable training. Theoretical analysis shows that the network achieves universal expressivity, interpretability, and hardware efficiency, capable of reproducing convolutional and attention mechanisms. Applications include high-speed image processing, interpretable artificial intelligence, and digital hardware acceleration, offering promising future research directions.

Coarse-grained reconfigurable arrays (CGRAs) have emerged as promising candidates for digital signal processing, biomedical, and automotive applications, where energy efficiency and flexibility are paramount. Yet existing CGRAs suffer from the Amdahl bottleneck caused by constrained control handling via either off-device communication or expensive tag-matching mechanisms. More importantly, mapping control flow onto CGRAs is extremely arduous and time-consuming due to intricate instruction structures and hardware mechanisms. To counteract these limitations, we propose Raccoon, a portable and lightweight framework for CGRAs targeting vast control flows. Raccoon comprises a comprehensive approach that spans microarchitecture, HW/SW interface, and compiler aspects. Regarding microarchitecture, Raccoon incorporates specialized infrastructure for branch- and loop-level control patterns with concise execution mechanisms. The HW/SW interface of Raccoon includes well-characterized abstractions and instruction sets tailored for easy compilation, featuring custom operators and architectural models for control-oriented units. On the compiler front, Raccoon integrates advanced control handling techniques and employs a portable mapper leveraging reinforcement learning and Monte Carlo tree search. This enables agile mapping and optimization of the entire program, ensuring efficient execution and high-quality results. Through the cohesive co-design, Raccoon can empower various CGRAs with robust control-flow handling capabilities, surpassing conventional tagged mechanisms in terms of hardware efficiency and compiler adaptability. Evaluation results show that Raccoon achieves up to a 5.78x improvement in energy efficiency and a 2.24x reduction in cycle count over state-of-the-art CGRAs. Raccoon stands out for its versatility in managing intricate control flows and showcases remarkable portability across diverse CGRA architectures.

Variant calling, which identifies genomic differences relative to a reference genome, is critical for understanding disease mechanisms, identifying therapeutic targets, and advancing precision medicine. However, as two critical stages in this process, serial processing in local assembly and the computational dependencies in Pair-HMM make variant calling highly time-consuming. Moreover, optimizing only one of these stages often shifts the performance bottleneck to the other. This article observes that the similarity between reads allows parallel processing in the local assembly and that alignment information from the local assembly can significantly diminish the burdensome computations in Pair-HMM. Accordingly, this article co-optimizes the software and hardware for both steps to achieve the best performance. First, we collect k-mer locations in each read during the local assembly process and utilize the similarity between reads to make it parallel. Second, we propose the mPair-HMM algorithm, leveraging location information to split a Pair-HMM computation task into multiple independent sub-tasks, improving the computation's parallelism. To fully exploit the parallelism stemming from the novel algorithms, we propose an end-to-end accelerator VCAx for variant calling that accelerates both stages in collaboration. Evaluation results demonstrate that our implementation achieves up to a 7x speedup over the GPU baseline for local assembly and a 3.16x performance improvement compared to the state-of-the-art ASIC implementation for Pair-HMM.

With the widespread use of large language models (LLMs), and with the privacy and cost concerns on cloud-based services, vendors are now pushing LLM inference to consumer devices. However, current attempts only enable real-time inference of low-quality small-sized LLMs. Large-sized LLMs have to load most of their weights from Flash storage for every execution iteration, which dominates the execution time of both the prefill and the generation phase. This performance bottleneck is attributed to both the low internal Flash memory bandwidth and the low transmission bandwidth between Flash and the Neural Processing Unit (NPU). To tackle these two challenges, we present Lincoln, a device-architecture co-design solution with LPDDR-interfaced, Compute-Enabled Flash Memory. On the device level, we boost the Flash internal bandwidth by improving upon existing array shrinking methods, to enable lower read latency and more parallel Flash planes within each Flash die. We specifically leverage 3D hybrid bonding, which is already adopted in consumer Flash products, to maintain high area efficiency and low density loss. On the architecture level, to leverage such increased internal bandwidth for resolving the transmission bottleneck, we propose two solutions for the two distinct phases of LLMs. For the compute-intensive prefill phase, we let Flash devices use the existing high-speed LPDDR interface (originally for DRAM), which offers much higher transmission bandwidth to the NPU than the conventional Flash interface, while maintaining good cost and area efficiency. For the memory-intensive generation phase, we rely on hybrid-bonding-based near-Flash computing to fully utilize the internal Flash bandwidth, and further equip with speculative decoding to eventually reach the real-time latency goal. Our evaluation shows that Lincoln enables real-time inference, with up to 13.23x and 254.1x speedups for LLM prefill and generation phases over conventional SSD-based systems.

As emerging applications raise ever-boosting and varying computational demand, the reconfigurable accelerator is becoming prevalent due to balanced performance, efficiency, and flexibility. Although the functions of its processing elements (PEs) and interconnections can be defined by a high-level software program, the circuit parameters are mostly managed by hardware or the compiler, leaving opportunities for in-depth optimization and novel features. Considering that the circuit adjustment is of great value in terms of low power and security, this article presents a novel software-defined accelerator named cross-domain software-defined chip (CDSDC), of which most chip properties including circuit parameters, logic, and pipelines can be programmed synergistically by software at runtime. With this design scheme, CDSDC provides new features including: 1) dynamic pipeline-voltage-frequency scaling (DPVFS), which combines pipeline reconfiguration with voltage-frequency scaling to generate an optimal chip configuration for various applications; 2) intrinsic physical unclonable function (PUF), which leverages the uniform PEs as measured circuit delay elements by adjusting the circuit parameters, extracting the entropy of manufacturing process variation, and taking response bits as a PUF; and 3) device-binding confidential configuration, which uses the intrinsic PUF and ASCON algorithm to encrypt/decrypt configuration. The CDSDC has been implemented in silicon as a 28-nm Taiwan Semiconductor Manufacturing Company (TSMC) HPC+ 1P8M 6-mm(2) test chip, operating at peak 400 MHz and 0.9 V, achieving a peak energy efficiency of 51 GOPS/W. It improves performance and efficiency for cross-domain patterns of computation by DPVFS. It improves hardware security against reverse engineering attacks by using intrinsic PUF and device-specific encrypted configuration flow.

Recent advancements in deoxyribonucleic acid (DNA) sequencing have brought about a significant paradigm shift in genome analysis, moving from linear approaches to pangenome graphs. Pangenome analysis demands powerful computation capabilities to handle graph data structures, which are irregular and complex, as well as the flexibility to adapt to various algorithms and data types. This article presents the first silicon accelerator for pangenome read mapping. The 5.9-mm(2) 822-mW application-specific integrated circuit (ASIC) accelerator includes a dedicated graph mapping engine (GME) that leverages domain-specific characteristics to parallelize computations. It achieves a throughput of 151.8 Mbp/s and an energy efficiency of 239 bp/mu J in pangenome read mapping. Moreover, its dynamic reconfigurability and pipeline bubble hiding technique allow it to efficiently adapt to multiple mapping schemes with improved hardware utilization. It is backward compatible with conventional short-read mapping and offers up to 2.24x area efficiency and 3.65x energy efficiency compared to state-of-the-art short-read mapping silicon accelerators while maintaining an accuracy comparable with standard software packages.

Deep learning (DL) is widely used for MRI reconstruction and leverages significant promotion. However, the existing DL-based methods still have some weaknesses. First, the information of the original input images and the extracted features of the shallow network are gradually weakened or even lost due to the deepening of the deep neural network, which is not thoroughly utilized during the reconstruction process. Second, due to the limitation of computation, most attention-based methods adopt self-attention layers on reduced-resolution images of U-shaped networks, which leads to the loss of information. Moreover, these approaches ignore the distinction between global dependencies and local region representations. In this paper, a novel detail-enhanced MR reconstruction network, termed DE-Net, is proposed to handle these limitations. Within, a proposed dense connection architecture is used as the backbone module for feature fusion and information reuse, to preserve the detailed information of initial images and extracted features. Meanwhile, a global–local dependent attention (GLDA) mechanism is designed to capture richer contextual associations on both global and local level while retaining the resolution, which further force the reconstruction on the relevant regions with complex structures according to contextual information. Comprehensive experiments on two benchmarks show that our proposed DE-Net outperforms all the baselines and achieves remarkable improvement in texture structure preservation and artifacts reduction.

With the unprecedented explosive growing amount of global data, the development of computing chips, which encounter bottlenecks such as power wall and memory wall, cannot satisfy the demanding requirement. This work proposes a software-defined process-near-memory (SDPNM) computing architecture implemented using 3D hybrid bonding integration. The software-defined chip architecture, featuring spatial computations and dynamic reconfiguration, innovates in a top-down manner to achieve high energy efficiency while maintaining flexibility after fabrication. The process-near-memory integration further advances the SDNPM chip in a bottom-up way to reduce the energy consumption of data movement while improving the bandwidth. Utilizing a relatively mature fabrication and bonding process can result in feasible solutions for both data-intensive and compute-intensive applications including digital signal processing and artificial intelligence. The logic die is fabricated in the SMIC 40 nm process and the DRAM die is fabricated in the PSMC 25 nm process. The hybrid bonding is implemented by XMC. The experimental results show that the energy efficiency of the proposed SDPNM chip is 33.1× better than the state-of-the-art FPGA ranging from 8.2× to 104.1×.

White-box cryptography (WBC) seeks to protect secret keys even if the attacker has full control over the execution environment. One of the techniques to hide the key is space hardness approach, which conceals the key into a large lookup table generated from a reliable small block cipher. Despite its provable security, space-hard WBC also suffers from heavy performance overhead when executed on general purpose hardware platform, hundreds of magnitude slower than conventional block ciphers. Specifically, recent studies adopt nested substitution permutation network (NSPN) to construct dedicated white-box block cipher [BIT16], whose performance is limited by a massive number of rounds, nested loop dependency and high-dimension dynamic maximal distance separable (MDS) matrices. To address these limitations, we put forward UpWB, an uncoupled and efficient accelerator for NSPN-structure WBC. We propose holistic optimization techniques across timing schedule, algorithms and operators. For the high-level timing schedule, we propose a fine-grained task partition (FTP) mechanism to decouple the parameteroriented nested loop with different trip counts. The FTP mechanism narrows down the idle time for synchronization and avoids the extra usage of FIFO, which efficiently increases the computation throughput. For the optimization of arithmetic operators, we devise a flexible and vectorized modular multiplier (VMM) based on the complexity-reduced Montgomery algorithm, which can process multi-precision variable data, multi-size matrix-vector multiplication and different irreducible polynomials. Then, a configurable matrix-vector multiplication (MVM) architecture with diagonal-major dataflow is presented to handle the dynamic MDS matrix. The multi-scale (Inv)Mixcolumns are also unified in a compact manner by intensively sharing the common sub-operations and customizing the constant multiplier. To verify the proposed methodology, we showcase the unified design implementation for three recent families of WBCs, including SPNbox-8/16/24/32, Yoroi-16/32 and WARX-16. Evaluated on FPGA platform, UpWB outperforms the optimized software counterpart (executed on 3.2 GHz Intel CPU with AES-NI and AVX2 instructions) by 7x to 30x in terms of computation throughput. Synthesized under TSMC 28nm technology, 36x to 164x improvement of computation throughput is achieved when UpWB operates at the maximum frequency of 1.3 GHz and consumes a modest area 0.14 mm2. Besides, the proposed VMM also offers about 30% improvement of area efficiency without pulling flexibility down when compared to state-of-the-art work.