The goal of the HARPA solution is to overcome the performance variability (PV) by enabling next-generation embedded and high-performance platforms using heterogeneous many-core processors to provide cost-effectively dependable performance: the correct functionality and (where needed) timing guarantees throughout the expected lifetime of a platform. This must be accomplished in the presence of cycle-by-cycle performance variability due to time-dependent variations in silicon devices and wires under thermal, power, and energy constraints. The common challenge for both embedded and high-performance systems is to harness the unsustainable increases in design and operational margins and yet provide dependable performance. For example, resources that are statically determined based on worst-case execution time for real-time applications or lower clock frequency to satisfy excessive timing margins in high-performance processors.

Convenient access to a complex benchmarking and monitoring tool was the main motivation for implementation of the proposed benchmarking tool. This paper provides a brief summary of its design and implementation. Its main purpose is to test an experimental server-side navigation service which has to comply to a multi-criteria service level agreement. The service is deployed on a heterogenous high performance computing infrastructure which is monitored by the tool. Consistent test environment is provided by the tool for transparent analysis and optimization of the service performance.

Continuously increasing application demands on both High Performance Computing (HPC) and Embedded Systems (ES) are driving the IC manufacturing industry on an ever-lasting scaling of devices in silicon. Nevertheless, integration and miniaturization of transistors comes with an important and non-negligible trade-off: time-zero and time-dependent performance variability. Increasing guard-bands to battle variability is not scalable, since worst-case design margins are prohibitive for downscaled technology nodes. This paper discusses the FP7-612069-HARPA project of the European Commission which aims to enable next-generation embedded and high-performance heterogeneous many-cores to cost-effectively confront variations by providing Dependable-Performance: correct functionality and timing guarantees throughout the expected lifetime of a platform under thermal, power, and energy constraints. The HARPA novelty is in seeking synergies in techniques that have been considered virtually exclusively in the ES or HPC domains (worst-case guaranteed partly proactive techniques in embedded, and dynamic best-effort reactive techniques in high-performance).

An increasing number of High-Performance Applications demand some form of time predictability, in particular in scenarios where correctness depends on both performance and timing requirements, and the failure to meet either of them is critical. Consequently, a more predictable HPC system is required, particularly for an emerging class of adaptive real-time HPC applications. Here we present our runtime approach which produces the results in the predictable time with the minimized allocation of hardware resources. The paper describes the advantages in terms of execution time reliability and the trade-offs regarding power/energy consumption and temperature of the system compared with the current GNU/Linux governors.

For lossless data compression of the texts of natural language and for achieving better compression ratio we can use linguistic and grammatical properties extracted from the text analysis. This work deals with usage of word order, word categories and grammatical rules in sentences and sentence units in Czech language. Special grammatical properties of this language which are different from for example English language are used here. Further, there is an algorithm designed for searching similarities in analyzed sentence structures and its next processing to final compressed file. For analysis of the sentence units a special tool is used which allows parsing on more levels.