Well-known approaches to person identification (PID) from afar are based on face recognition or gate detection using a camera. The former is privacy-violating while both suffer from camera poor performance in low/intense light and harsh weather conditions. Mm-wave radars, on the other hand, are proven to be a privacy-friendly robust solution in many applications, including object detection/classification. In this paper, we propose two approaches to radar-based PID using micro-Doppler (MD) analysis and inverse synthetic aperture radar (ISAR). The proposed approaches are evaluated in PID within a family of five members. The results show the great potential of the mm-wave technology in PID applications.

In this article, two implementations of a radar-based human-robot interface are presented. These implementations represent two classes of inference approaches that are investigated in the radar group at imec. The first class exploits traditional machine learning classification techniques. The second class uses spiking neural networks. The machine learning classification system presented in this article supports nine gestures and achieves a gesture classification accuracy of 93%. This compares to an accuracy of 98% for our spiking neural network system operating on four gestures. Based on public data sets, this accuracy remains, while exceeding published state of the art results. Misclassification is however significant, which is still precluding safety critical interactions when using a single radar sensor. As proof-of-concept, a discrete control of a robot will be demonstrated by means of radar-based gesture recognition using five gestures. We present the main concepts of this demonstrator. For pre-validation, we use emulation of the gesture recall statistics and timing characteristics to model the radar part.

This article presents a MATLAB-to-C compiler that exploits custom instructions present in state-of-the-art processor architectures and supports semi-automatic vectorization. A parameterized processor model is used to describe the target instruction set architecture to achieve user-friendly retargetability. Custom instructions are represented via specialized intrinsic functions in the generated code, which can then be used as input to any C/C++ compiler supporting the target processor. In addition, the compiler supports the generation of data parallel/vectorized code through the introduction of data packing/unpacking statements. The compiler has been used for code generation targeting ARM and x86 architectures for several benchmarks. The vectorized code generated by the compiler achieves an average speedup of 4.1× and 2.7× for packed fixed and floating point data, respectively, compared to scalarized code for ARM architecture and an average speedup of 3.1× and 1.5× for packed fixed and floating point data, respectively, for x86 architecture. Implementing data parallel instructions directly in the assembly code would have required a lot of design effort, and it would not been sustainable across evolving platform variants. Thus, the compiler can be employed to efficiently speed up critical sections of the target application. The compiler is therefore potentially employable to raise the design abstraction and reduce development time for both embedded and general-purpose applications.

The goal of the HARPA solution is to overcome the performance variability (PV) by enabling next-generation embedded and high-performance platforms using heterogeneous many-core processors to provide cost-effectively dependable performance: the correct functionality and (where needed) timing guarantees throughout the expected lifetime of a platform. This must be accomplished in the presence of cycle-by-cycle performance variability due to time-dependent variations in silicon devices and wires under thermal, power, and energy constraints. The common challenge for both embedded and high-performance systems is to harness the unsustainable increases in design and operational margins and yet provide dependable performance. For example, resources that are statically determined based on worst-case execution time for real-time applications or lower clock frequency to satisfy excessive timing margins in high-performance processors.

This article discusses a MATLAB-to-C vectorizing compiler that exploits custom instructions, for example, for Single Instruction Multiple Data (SIMD) processing and instructions for complex arithmetic present in Application-Specific Instruction Set Processors (ASIPs). Custom instructions are represented via specialized intrinsic functions in the generated code, and the generated code can be used as input to any C/C++ compiler supporting the target processor. Furthermore, the specialized instruction set of the target processor is described in a parameterized way using a target processor-independent architecture description approach, thus allowing the support of any processor. The compiler has been used for the generation of application code for two different ASIPs for several benchmarks. The code generated by the compiler achieves a speedup between 2× --74× and 2× --97× compared to the code generated by the MathWorks MATLAB-to-C compiler. Experimental results also prove that the compiler efficiently exploits SIMD custom instructions achieving a 3.3 factor speedup compared to cases where no SIMD processing is used. Thus the compiler can be employed to reduce the development time/effort/cost and time to market through raising the abstraction of application design in an embedded systems/system-on-chip development context.

This paper presents a 2×14bit cartesian Direct Digital RF Modulator (DDRM) in 28nm CMOS. Both AM and PM calibration circuits are introduced to relax matching requirements of the DDRM units which results in a compact and efficient implementation. The DDRM features a memoryless current source based unit cell to avoid complex dynamic digital predistortion (DPD) algorithms. All the units can be tuned to less than 0.4LSB from their nominal value. When combined with memoryless DPD, ACLR and C-IM3 better than -60dBc is obtained at ~0dBm output power.

This paper discusses a MATLAB to C compiler exploiting custom instructions such as instructions for SIMD processing and instructions for complex arithmetic present in Application Specific Instruction Set Processors (ASIPs). The compiler generates ANSI C code in which the processor's special instructions are represented via specialized intrinsic functions. By doing this the generated code can be used as input to any C/C++ compiler. Thus the proposed compiler allows the description of the specialized instruction set of the target processor in a parameterized way allowing the support of any processor. The proposed compiler has been used for the generation of application code for an ASIP targeting DSP applications. The code generated by the proposed compiler achieves a speed up between 2x-30x on the targeted ASIP for six DSP benchmarks compared to the code generated by Mathworks MATLAB to C compiler. Thus the proposed compiler can be employed to reduce the development time/effort/cost and time to market by raising the abstraction of application design in an embedded systems / system-on-chip development context while still improving implementation efficiency.

An important challenge in the domain of vehicular ad hoc networks (VANET) is the scalability of data dissemination. Under dense traffic conditions, the large number of communicating vehicles can easily result in a congested wireless channel. In that situation, delays and packet losses increase to a level where the VANET cannot be applied for road safety applications anymore. This paper introduces scalable data dissemination in vehicular ad hoc networks (SDDV), a holistic solution to this problem. It is composed of several techniques spread across the different layers of the protocol stack. Simulation results are presented that illustrate the severity of the scalability problem when applying common state-of-the-art techniques and parameters. Starting from such a baseline solution, optimization techniques are gradually added to SDDV until the scalability problem is entirely solved. Besides the performance evaluation based on simulations, the paper ends with an evaluation of the final SDDV configuration on real hardware. Experiments including 110 nodes are performed on the iMinds w-iLab.t wireless lab. The results of these experiments confirm the results obtained in the corresponding simulations.

Emerging high throughput wireless communication standards, such as LTE/LTE-A and IEEE 802.11ac, impose exciting challenges on SDR baseband implementations. Our work explores the feasibility of SDR baseband for the most demanding-modes in those emerging high throughput standards. On a customized C programmable SDR baseband processor (with compiler support), we have accomplished realtime inner receiver implementations for Cat-4/5/7 LTE/LTE-A UE and up to the 80MHz 4 × 4 mode of IEEE 802.11ac. The implemented inner receiver includes all essential synchronization and data detection functionalities, including coarse CFO estimation/compensation, I/Q imbalance estimation/compensation, OFDM(A) demodulation, channel estimation, fine SCO/CFO estimation/compensation, channel tracking, MIMO channel processing, MIMO data detection, LLR generation, etc..

The Chinese Digital Television Terrestrial Broadcasting System has a complex PHY layer definition with many different modes including two different block transmission schemes (OFDM and SC) and three different known symbol padding cyclic extensions, some of which with phase rotation between blocks that break the cyclicity. The block sizes with or without cyclic extension are “non power of two” numbers. This plurality of modes and the unusual block sizes make the design of a signal processing architecture very difficult. In addition, the known symbol padding extensions are intended for channel estimation but have poor auto-correlation properties; hence the channel estimation in long multipath channels is degraded and not suitable for high order constellations. We have designed a novel unified receiver architecture supporting all modes of this broadcasting system, capable to start from a poor initial channel estimation. We describe in detail this architecture and provide simulation results supporting our system choices.

The rapidly evolving and diversifying wireless landscape demands highly flexible wireless chipsets. Due to the ultimate programmability, SDR solutions are becoming more and more attractive. However, the programmability overhead is still a concern for the silicon area cost of SDR solutions. In this work, we prove that, with algorithm and architecture co- design, SDR solutions can be very competitive even when compared to highly optimized ASICs. Specifically, we show a baseband processor design that can support ISDB-T, DVB-T and ATSC, but the area cost is still comparable to the combination of ASICs which handle the three terrestrial digital TV standards respectively.

Two quite different tools are normally used in the research of Vehicular Ad Hoc Networks (VANET). Simulators are practical and cost-efficient, but are not entirely accurate representations of the real life situation. Field operational tests (FOT) provide exactly the opposite characteristics. A wireless testbed is situated somewhere in between, but has not yet been applied in VANET research. In this paper it is researched if such a wireless testbed could be suitable for this kind of research. The corresponding requirements are defined, and it is investigated how the generic indoor wireless testbed w-iLab.t can be made compliant using only software adjustments. Proposed techniques are an approximation of the IEEE 802.11p standard using. 11a hardware, the emulation of mobility based on link impairment, and the use of low transmit power together with manual topology configuration. These techniques are generic, and can be applied on other wireless testbeds. However, some limitations have to be taken into account. For the highway setting, w-iLab.t can provide densities up to 25% of the actual maximum VANET density in intense but flowing traffic. Experiments representing urban scenarios are labour intense and limited in topology size. Based on these observations, it is concluded that a generic wireless testbed is a valuable but complementary tool in VANET research.

With the soaring development cost of deep sub-micron silicon and the fast-growing diversity in wireless communications, software defined baseband becomes more and more important for handheld devices. However, most software defined receivers reported in previous literatures are still far away from fulfilling the requirement of emerging wireless standards such as the LTE-Advanced. The category-E User Equipment (UE) defined in LTE-Advanced, as the most demanding category for handheld devices, requires processing 2 concurrent data streams at around 300Mbps aggregated throughput. It is not clear whether SDR baseband processors can tackle this challenge. In our work, we explore the feasibility for software defined baseband for LTE-Advanced. With a highly customized SDR baseband processor, we have recently accomplished a software defined downlink inner receiver for Category-E LTE-Advanced UE. The implemented inner receiver includes fully fledged synchronization and data detection functionalities, including coarse CFO estimation/compensation, I/Q imbalance estimation/compensation, OFDMA demodulation, channel estimation, fine SCO/CFO estimation/compensation, MIMO channel processing, MIMO data detection and LLR generation. This paper is intended to bring an overview for the work and emphasizes key aspects that enable the feasibility of the work. In this paper, we will introduce the algorithm and processor architecture co-design flow, overall receiver functionalities, important optimizations and implementation results.

We address the problem of channel tracking in fast vehicular environments for OFDM systems. In modern vehicular OFDM systems such as the IEEE802.11p, the preamble-based channel estimation is not sufficient to guarantee a good equalization until the end of the burst. Indeed, at urban and highway vehicular speeds, a conventional OFDM receiver generates a large number of errors after only a few OFDM symbols and the bit and packet error rate curves show unacceptable flooring. In addition, the number of pilot sub-carriers during the burst is too small to accurately track the channel variations. To alleviate this, we propose an advanced receiver scheme that updates the channel during the burst in a decision-directed fashion. We show that this technique alone is not sufficient and that it must be complemented with channel smoothing to perform satisfactorily at low SNRs. Finally, we also analyze how the system can be further improved with spatial diversity. Simulation results are provided to illustrate the performance of our novel receiver design and some complexity reduction techniques are described.

Digital wireless communication has played a key role in our lives for more than one decade. Over the last decade we have observed rapid increase of the variability within and in the number of standards in the wireless domain and rapidly increasing computational demand for those applications. Embedded solutions for those systems require highly flexible programmable multi-core low power Software Defined Radio (SDR) platforms. Such platforms exist, however an efficient mapping flow from the algorithmic specification towards the implementation of the algorithm is lacking.In this paper we present a complete mapping flow from algorithmic specification to parallel implementation on an SDR platform. The flow is supported by industrial and in-house tools for the critical parts of the mapping path. Local loops in the flow are avoiding global iterations and allow fast exploration at different stages. Results obtained by applying the flow on an industrial-strength test-vehicle, namely a 40 MHz MIMO SDM-OFDM baseband subsystem are discussed at the end of the paper.

This paper describes the implementation of a flexible Turbo and LDPC outer modem engine which is capable of supporting the WiFi(802.11n), WiMax(802.16e) and 3GPP-LTE standard on the same hardware resources. The chip is implemented in a 65nm CMOS technology and occupies 10.37 mm(2). The decoder flexibility is offered by means of an application-specific instruction-set processor (ASIP), with full datapath reuse between Turbo and LDPC decoding. The encoders are dedicated ASIC datapaths. The maximum clock speed can be set to 320 MHz allowing a decoder output rate for a single iteration in excess of 140 Mbps for Turbo and 640 Mbps for LDPC with a maximum power consumption of 675 mW. The architecture template has been extended to support other standards like the DVB-S2/T2 LDPC decoding as well.

This paper presents a memory organization for SDR inner modem baseband processors that focus on exploiting ILP. This memory organization uses power-efficient, single-ported, interleaved scratch-pad memory banks to provide enough bandwidth to a high-ILP processors. A system of queues in the memory interface is used to resolve bank conflicts among the single-ported banks, and to spread long bursts of conflicting accesses to the same bank over time. Bank address rotation is used to spread long bursts of conflicting accesses over multiple banks. All proposed techniques have been implemented in hardware, and are evaluated for a number of different wireless communication standards. For the 11a|n benchmarks, the overhead of stall cycles resulting from unresolved bank conflicts can be reduced to below 2% with the proposed organization. For 3GPP-LTE, the most demanding wireless standard we evaluated, the overhead is reduced to less than 0.13%. This is achieved with little energy and area overhead, and without any bank-aware compiler support.

In the past research has been done on cooperative systems resulting in, among others, the CALM architecture which is used in NextGenITS. The project focuses on the scalability issues of routing protocols and energy optimizations for cooperative vehicular ad hoc network (VANET) systems. The resulting solutions will be simulated using TraNS and Nsclick. Afterwards the architecture and routing protocols will be tested in real life on small and large scale.