The explosive growth of data-intensive applications and Generative AI (GAI) workloads has led to unprecedented demands on computing resources. Virtual Machine (VM) migration is pivotal in dynamically adjusting resource distribution across workloads. However, traditional reactive approaches often fall short in adapting to network changes and dynamic workloads. This paper presents a Digital Twin (DT) framework integrated with a data center to enhance resource utilization. The framework combines real-time monitoring, time-series forecasting, and Mixed-Integer Linear Programming (MILP) optimization to predict future bandwidth demands, CPU utilization, and memory usage, thereby determining optimal VM migration and placement strategies. Our analysis reveals that integrating forecasting with optimization reduces CPU load variance across servers by up to 50%. Compared to prior reactive or heuristic-based methods, our forecast-aware optimization framework achieves significantly more uniform resource distribution. Furthermore, capping server CPU load at 50% of capacity nearly eliminates variance, underscoring the effectiveness of the proposed model in stabilizing data center workloads.

Machine learning (ML) is a powerful tool for solving stochastic optimization problems. The aerospace and defense sectors have a number of stochastic optimization problems that would benefit from the application of ML; however, people often have difficulties interpreting solutions arrived at via ML, which undermines trust, producing an obstacle to widespread adoption in these sectors. This paper introduces the Self-Explaining Decision Architecture (SEDA) for ML-based decision-making systems capable of generating intuitive explanations for their decisions in real time. SEDA makes use of a feature extraction subsystem and a sequence interpretation subsystem to identify patterns in data followed by a decision generation subsystem that determines appropriate actions based on those patterns. Internal state information from each of these subsystems is used to generate explanations of the system’s decisions. Using this information to create explanations provides insight as to the data elements the system focused on when making decisions as well as the reasoning that was used. As a proof-of-concept, we present a first implementation of SEDA using start-of-the-art deep learning components including a combined convolutional neural network and long short-term memory network with attention mechanisms and demonstrate its use on both standard and custom datasets.

The DoD is increasingly employing agile methods in efforts to rapidly produce software. However, the specific domain of agile methodologies as applied to the sustainment of embedded systems remains in need of further research. One initial area examined here is the relationship between agile principles and the policies and practices used by DoD sustainment organizations. It is shown that current sustainment policy for the Air Force Sustainment Center is compatible with agile principles. Challenges specific to sustainment operations can be resolved through careful consideration of the scope and organizational levels at which agile principles and practices are implemented.

Performance and robustness of dynamic scheduling algorithms are evaluated in the presence of errors in the tasks’ resource requirements. Previous work found that incorporating task completion events from the actual distributed system into the algorithms’ model of the system was crucial for achieving robustness. In the present paper, various degrees of feedback, rather than simply all-or-none, are evaluated using the same simulated studies as in previous work and a proposed strategy for biasing model tasks’ resource requirement information is proposed in order to counteract the most egregious effects of model error on performance.

Scheduling algorithms used for dynamic scheduling of tasks in a distributed system are generally evaluated on their performance, i.e., their degree of achieving a desired outcome or metric. They may also be evaluated on the basis of their robustness, which is the degree to which the scheduling algorithm is able to achieve similar performance in the present of error in the task requirements or system resource availability. In this paper, a modelbased framework for evaluating and improving scheduling algorithms’ performance and robustness is proposed. We also demonstrate through simulated results how system feedback can be incorporated to increase robustness of four evaluated scheduling algorithms.

Using Graphics Processing Units (GPUs) to solve general purpose problems has received significant attention both in academia and industry. Harnessing the power of these devices however requires knowledge of the underlying architecture and the programming model. In this paper, we develop analytical models to predict the performance of GPUs for computationally intensive tasks. Our models are based on varying the relevant parameters - including total number of threads, number of blocks, and number of streaming multi-processors - and predicting the performance of a program for a specified instance of these parameters. The approach can be used in the context of heterogeneous environments where distinct types of GPU devices with different hardware configurations are employed.

The availability and utility of large numbers of Graphical Processing Units (GPUs) have enabled parallel computations using extensive multi-threading. Sequential access to global memory and contention at the size-limited shared memory have been main impediments to fully exploiting potential performance in architectures having a massive number of GPUs. After performing extensive study of data structures and complexity analysis of various data access methodologies, we propose novel memory storage and retrieval techniques that enable parallel graph computations to overcome the above issues. More specifically, given a graph G = (V,E) and an integer k <= ｜V｜, we provide both storage techniques and algorithms to count the number of: a) connected subgraphs of size k; b) k cliques; and c) k independent sets, all of which can be exponential in number. Our storage techniques are based on creating a breadth-first search tree and storing it along with non-tree edges in a novel way. Our experiments solve the above mentioned problems by using both naïve and advanced data structures on the CPU and GPU. Speedup is achieved by solving the problems on the GPU even using a brute-force approach as compared to the implementations on the CPU. Utilizing the knowledge of BFS-tree properties, the performance gain on the GPU increases and ultimately outperforms the CPU by a factor of at least 5 for graphs that completely fit in the shared memory and by a factor of 10 for larger graphs stored using the global memory. The counting problems mentioned above have many uses, including the analysis of social networks.

An approach to efficiently schedule heterogeneous tasks in a distributed environment is presented. Given a set of tasks each with varied CPU and main memory requirements, and a cluster of compute nodes (which are significantly less than the number of tasks), our goal is to find an assignment of tasks to compute nodes such that the total time taken to execute all the tasks is minimized. The task assignment problem in general is NP-Hard and it is further complicated by the changing dynamics (changes to CPU and main memory availability) of the compute nodes. Our solution methodology involves the following: a) develop an analytical model that will determine the upper and lower bounds on the efficiency of a compute node, given the number of processor cores in each compute node, the number of threads in execution, aggregate CPU load, and main memory and CPU availability and b) using these bounds and some properties of the tasks (CPU and main memory utilization values) two tasks assignment models are proposed and extensively evaluated empirically. The key challenge is to determine the CPU availability for a new task. We have proposed a new model (composite) to derive these bounds and experiments have shown that our derived bounds are consistently tight. For all our empirical evaluations on UNIX systems, we have used tasks that are both synthetic (allowing us to control the CPU and memory requirements) for validating composite model and realworld tasks such as prime number generator, merge sort, image rendering, and others for validating task assignment models.

Digital television systems have a clear disadvantage relative to analog systems in users' quality of experience, most notably in the time required to change channels, or zap time. The goal of this research is to improve the performance of a multicasting IPTV network, both in user experience and in resource consumption. We formulate the problem of assigning IPTV clients to servers as an integer programming model, in variants which minimize channel-change times, overall network capacity consumption, or both. This problem is shown to be computationally hard, and the performance of the models is tested on problems of different sizes. Polynomial-time heuristics are presented which address a relaxed version of the problem, and the performance of these heuristics is measured.

Techniques for predicting the availability of CPU resources associated with the execution of multiple concurrent Java threads on a multi-core architecture are introduced. Prediction of CPU availability is important in the context of making thread assignment and scheduling decisions. Theoretically derived upper and lower bound formulas for estimating CPU availability are introduced. Input parameters to the formulas include: number of cores; number of threads; and the unloaded CPU usage factor for each thread. Extensive experimental studies and statistical analysis are performed to validate the theoretical bounds and provide a basis for an empirical model for predicting CPU availability. To facilitate scientific and controlled empirical evaluation, synthetically generated threads are employed that are parameterized by their unloaded CPU usage factor, defined as the fraction of time a thread spends utilizing CPU resources on an unloaded system.

The Gozer workflow system is a production workflow authoring and execution platform that was developed at RiskMetrics Group. It provides a high-level language and supporting libraries for implementing local and distributed parallel processes. Gozer was developed with an emphasis on distributed processing environments in which workflows may execute for hours or even days. Key features of Gozer include: implicit parallelization that exploits both local and distributed parallel resources; survivability of system faults/shutdowns without losing state; automatic distributed process migration; and implicit resource management and control. The Gozer language is a dialect of Lisp, and the Gozer system is implemented on a service-oriented architecture.

Embedded systems often must adhere to strict size, weight, and power (SWAP) constraints and yet provide tremendous computational throughput. Increasing the difficulty of this challenge, there is a trend to utilize commercial-off-the-shelf (COTS) components in the design of such systems to reduce both total cost and time to market. Employment of COTS components also promotes standardization and permits a more generalized approach to system evaluation and design than do systems designed at the applicatiospecific-integrated-circuit (ASIC) level. The computationally intensive application of synthetic aperture radar (SAR) is by nature a high-performance embedded application that lends itself to parallelization. A system performance model, in the context of SWAP, is developed based on mathematical programming. This work proposes an optimization technique using a combination of constrained nonlinear and integer programming.

Computational efficiency is of great significance for high-performance embedded applications. The work here develops and evaluates a genetic-algorithm-based (GA-based) optimization technique for the scheduling of messages for a class of parallel embedded signal processing techniques known as space–time adaptive processing (STAP). The GA-based optimization is performed off-line, resulting in static schedules for the compute nodes of the parallel system. These static schedules are utilized for the on-line implementation of the parallel STAP application. The primary motivation and justification for devoting significant off-line effort to solving the formulated scheduling problem is the resulting reduction of hardware resources required for the actual on-line implementation. Numerical studies illustrate that reductions in hardware requirements of around 50% can be achieved by employing the results of the proposed scheduling techniques. This reduction in hardware requirement is of critical importance for STAP, which is typically an airborne application in which the size, weight, and power consumption of the computational platform are severely constrained.

A class of reconfigurable processors is introduced in which support for an instruction set is distributed among a collection of pre-defined configurations. For this new class of reconfigurable processors, there is assumed to be a pre-defined collection of configurations in which each configuration supports a subset of the overall instruction set. The union of all subsets of instructions, associated with the configurations, defines the instruction set supported by the reconfigurable processor. An objective for this class of reconfigurable processors is the support of popular commercial instruction set architectures with less hardware than required using existing static (i.e., non-reconfigurable) processors.

A microprocessor taxonomy is introduced based on whether: (1) the hardware is static or reconfigurable and (2) the code translation process is static or dynamic. The IBM DAISY and Transmeta Crusoe/spl trade/ microprocessors are reviewed. These static hardware microprocessors support a dynamic translation process to execute programs originally compiled for the PowerPC and Intel/spl reg/ X86 microprocessors, respectively. Inspired by features from both the DAISY and Crusoe/spl trade/ microprocessors, a conceptual design of a dynamically reconfigurable microprocessor is given. Driven by the results of a preliminary study, a specific approach to designing a reconfigurable microprocessor is presented. As a part of this approach, the concept of partitioning the instruction set of a microprocessor in order to support an application, instead of partitioning the functionality of the application, is developed.

Designing chips for lower power applications is one ofthe most important challenges faced by the VLSI designers.Since the power consumed by I/O pins of a CPU is a significant source of power consumption, work has been doneon developing encoding schemes for reducing switching activity on external buses. In this paper, we propose a newcoding technique, namely, the Dynamic Coding Scheme,for low-power data bus. Our method considers two logical groupings of the bus lines, each being a permutation ofthe bus lines, and dynamically selects that grouping whichyields the minimum number of transitions.

The power consumed by a combinational circuit is dictated by the switching activities of all signals associated with the circuit. An analytical approach is proposed for calculating signal activities for combinational circuits. The approach is based on a Markov chain signal model, and directly accounts for correlations present among the signals. The accuracy of the approach is verified by comparing signal activity values calculated using the proposed approach with corresponding values produced through simulation studies. It is also demonstrated that the proposed approach is computationally efficient.

@‘‡rqrqÃ6i†‡…hp‡ The focus of this work involves the investigation of parallelization and performance improvement for a class of radar signal processing techniques known as space-time adaptive processing (STAP). STAP refers to an extension of adaptive antenna signal processing methods that operate on a set of radar returns gathered from multiple elements of an antenna array over a specified time interval. Because the signal returns are composed of range, pulse, and antenna-element samples, a three-dimensional (3-D) cube naturally represents STAP data. Typical STAP data cube processing requirements range from 10-100 giga floating point operations per second (Gflops). Imposed real-time deadlines for STAP applications restricts processing to parallel computers composed of numerous interconnected compute nodes (CNs). A CN has one or more processors connected to a block of shared memory. Developing a solution to any problem on a parallel system is generally not a trivial task. The overall performance of many parallel systems is highly dependent upon network contention. In general, the mapping of data and the scheduling of communications impacts network contention of parallel architectures. The primary goals of many applications implemented on parallel architectures are to reduce latency and minimize interprocessor communication time (IPC) while maximizing throughput. It is indeed necessary to accomplish these objectives in STAP processing environments. In most STAP implementations, there are three phases of computations, one for each dimension of the data cube (i.e., range, pulse, and channel). To reduce computational latency, the processing at each phase must be distributed over multiple CNs using a single program multiple data (SPMD) approach. Additionally, prior to each processing phase, the data set must be partitioned in a fashion that attempts to equally distribute the computational load over the available CNs. Because each of the three phases process a different dimension of the data cube, the data must be redistributed to form contiguous vectors of the next dimension prior to the next processing phase. This redistribution of data or distributed " corner-turn " requires IPC. Minimizing the time required for interprocessor communication helps maximize STAP processing efficiency. Driven by the need to solve complex real-time applications that require tremendous computational bandwidths such as STAP algorithms, commercial-off-the-shelf (COTS) embedded high-performance computing systems that emphasize upward scalability have emerged in the parallel processing environment. In a message passing parallel system, CNs are connected with each other via a common data communication fabric or interconnection network. For the purposes of discussion and …

An important consideration in the maximization of performance in parallel processing systems is scheduling the communication of messages during phases of data movement to reduce network contention and overall communication time. The work presented in this paper focuses on off-line optimization of message schedules for a class of radar signal processing techniques know as space-time adaptive processing on a parallel embedded system. In this work, a genetic-algorithm-based approach for optimizing the scheduling of messages is introduced. Preliminary results indicate that the proposed genetic approach to message scheduling can provide significant decreases in the communication time.

A prototype system is described that demonstrates the advantages and trade-offs associated with the combined use of different hardware technologies for two embedded radar processing applications. The primary metrics of interest are size, weight, and power utilizations. The system can be configured with FPGAs (field programmable gate arrays), DSPs (digital signal processors), and/or GPPs (general purpose processors). The two radar applications evaluated are SAR (synthetic aperture radar) and STAP (space-time adaptive processing). Although the prototype system is not evaluated through actual fielded studies, experiments involving continuous input streams at relatively high rates are conducted in the laboratory using stored and unprocessed radar data as input. The FPGA components of the prototype system are commercially available WildOne and WildForce boards (from Annapolis Microsystems) populated with 4000-series Xilinx parts. The WildForce boards each have four 4085-series FPGAs plus one control FPGA. The DSP/GPP components of the system are within a Mercury Race Multicomputer configured with both SHARC and PowerPC compute nodes. The Mercury system can be configured with up to eight PowerPC nodes and eight SHARC compute nodes (each SHARC compute node actually contains three SHARC DSP chips). An overview of the overall architecture is depicted in Figure 1. The source PC is responsible for initially loading unprocessed radar data (from disk) into a circular buffer within its main memory. Once the input data is loaded into the circular buffer, the source PC then continuously (and repeatedly) streams this data into the front-end FPGA subsystem, denoted as (F) in Figure 1. It was necessary to locate the input data in a large main memory buffer in order to achieve realistic data throughput rates, which would otherwise not be possible if the data were streamed directly from the disk of the source PC. All of the Annapolis FPGA boards are PCI-based and reside on the data source and/or data sink PCs. A total of four WildForce boards are available, and zero or more of these may reside on the source and sink PCs. The source and sink PCs also contain one WildOne board each. The WildOne boards are not used for computation, but handle the data communication (through the PCI bus) between the PCs and the FPGA subsystems. The data communication among all FPGA boards is through two types of 36-bit wide connectors, one called systolic and one called SIMD. The data communication between the front-end FPGA subsystem (F) and the DSP/GPP subsystem is a custom interface developed using the systolic connector from Annapolis and the RIN-T input device from Mercury. Similarly, the data communication between the DSP/GPP subsystem and the back-end FPGA subsystem (B) is through a custom interface developed using the ROUT-T output device from Mercury and the systolic connector from Annapolis. Figures 2 and 3 illustrate how the major computational components of the SAR and STAP applications can be mapped onto the prototype system. A candidate mapping is defined by assigning the computations of each major component to one or both of the symbols shown in each block (which correspond to one of the FPGA or DSP/GPP subsystems). Using SAR to illustrate, one mapping would be to perform all of the range compression on the front-end FPGA subsystem (F) and then perform all azimuth processing on the DSP/GPP subsystem. Another possible mapping is defined by using the FPGA subsystems and the DSP/GPP for both components of computation. It is also possible to use only the DSP/GPP subsystem for both components of computations. The SAR studies were designed by adapting the RASSP (Rapid Prototyping of Application Specific Signal Processors) benchmark developed originally by Lincoln Laboratory at MIT. The benchmark, which was originally implemented in serial C code, was first modified to execute on the parallel DSP/GPP subsystem. A data-streaming component was also added so that input data can be sent continuously from the data source of the prototype system. Core computations from the range compression and azimuth processing components were implemented for the FPGA subsystems. The STAP studies were designed by adapting the RT_STAP (Real Time STAP) benchmark developed originally at MITRE. This benchmark was already implemented for parallel execution on a PowerPC-based Mercury system. This implementation was expanded to also enable execution on SHARC compute nodes. The same basic data streaming component that was developed for SAR was also adapted to enable the STAP input data to be sent continuously from the data source. Finally, core computations from the range compression and weight computation components from the STAP processing flow were implemented for the FPGA subsystems. The size, weight, and power utilizations of various mappings and problem instances are under investigation. Initial indications are that heterogeneous configurations, which utilize two or more hardware technologies of the prototype system, are preferred over homogeneous configurations.