ARCHYTAS aims to design and evaluate nonconventional hardware accelerators, in particular, optoelectronic, volatile and non-volatile processing-in-memory, and neuromorphic, to tackle the power, efficiency, and scalability bottlenecks of AI with an emphasis on defense use cases (e.g., autonomous vehicles, surveillance drones, maritime and space platforms). In this paper, we present the system architecture and software stack that ARCHYTAS will develop to integrate and support those accelerators, as well as the simulation software needed for early prototyping of the full system and its components.
The growing complexity of applications combined with the need to execute them on resource-constrained platforms, demands highly efficient system-level optimization strategies. While advancements in hardware accelerators have improved performance, they remain insufficient without intelligent Resource Management (RM) that can dynamically adapt to the unique characteristics of both applications and hardware. Classical analytical models struggle to capture the intricate interactions in modern heterogeneous systems, prompting a shift toward machine learning (ML)-based RM approaches. This paper provides an in-depth analysis of the challenges and potential of applying ML to RM. We begin by presenting experimental examples that highlight the motivations for using ML and the challenges it presents. Two case studies - offline- and online-learning-based RM are discussed to illustrate the state-of-the-art approaches and their limitations. Finally, we outline the opportunities for future research directions to address open challenges and pave the way for efficient, adaptive, and reliable system-level optimization.
This paper introduces a high-precision, lowpower Bandgap Reference (BGR) circuit designed using UMC 28 nm CMOS technology. The proposed BGR circuit achieves a stable reference voltage of 0.647 V with a temperature coefficient of 17.69 ppm/degrees C across a temperature range of -40 degrees C to 125 degrees C. The utilization of advanced curvature compensation techniques involving subthreshold region MOSFET current, the design ensures minimal power consumption of 38.62 mu W. The optimized layout with 0.082 mm(2) area, minimizes parasitic effects and maintains robust signal integrity, making the circuit suitable for precision analog and low-voltage applications.
Assertion generation for Formal Verification (FV) needs an in-depth understanding of assertion language constructs, design fundamentals and RTL implementation techniques. Assertions are derived from a design’s natural language (NL) specification, but this is hindered by (i) NL ambiguity, leading to multiple interpretations, and (ii) the need to validate translations, as errors may occur. To address these issues, we propose LISA, an interactive framework leveraging large language models (LLMs), a formal verification tool, and human guidance. It systematically translates an NL specification into SystemVerilog Assertions (SVA) that accurately capture the intended behavior. LISA begins by breaking down complex NL descriptions into a structured verification plan using Chain-ofThought (CoT). It then generates SVAs for each item in the verification plan, formally verifies them using an FV tool, and analyzes statement coverage. For coverage gaps, LISA refines the assertions in an iterative feedback loop to enhance quality and correctness with the help of Retrieval Augmented Generation (RAG). We conduct a comprehensive LLM-assisted NL to SVA generation case study, producing syntactically correct SVAs with high statement coverage for the OpenTitan IPs, achieving 100% syntactic correctness with zero or one-shot prompting.
In recent years, in-memory computing has been extensively utilized for data-intensive applications due to its high speed and energy efficiency. Various memory technologies have been explored for this purpose, with Resistive Memory (RRAM) standing out due to its ability to naturally implement MultiplyAccumulate (MAC) operations, making it a promising solution for neural network acceleration. Additionally, RRAM is also applied in general logic computing applications. However, RRAM-based logic in-memory computing faces notable challenges, such as the need for repeated write operations, which leads to high latency and energy inefficiency. Furthermore, synthesized circuits often require mapping into large crossbars, reducing area efficiency. In this work, we introduce a novel logic in-memory computing framework designed to address these issues. Our proposed framework transforms the logic evaluation of AndInverter Graphs (AIGs) into MAC operations and binary step functions. This method eliminates the necessity for frequent write operations during the computing phase, thereby enhancing operational efficiency. Additionally, we propose two optimization techniques to achieve better area efficiency. Simulation results demonstrate that our proposed computing framework can perform logic evaluation without the need for writing during the computing phase. Furthermore, it achieves an average reduction of 86.13% in the Area-Latency-Product (ALP), a key metric for logic evaluation, compared to traditional designs.
This work presents novel and efficient architectures for modulo $2^{n}-4$ adders, modulo $2^{n}-4$ multipliers, and modulo $2^{n}-4$ residue generators that exploit the intrinsic characteristics of modulo $2^{n}-4$ arithmetic. The proposed designs are derived from existing architectures for modulo $2^{n-2}-1$ operations, supplemented with simple logic components, thereby enabling highly efficient VLSI implementations. Experimental comparisons validate that the proposed circuits offer substantial improvements in delay and area over previously reported designs.
As FinFET miniaturization approaches scaling limits, investigating 3D transistor structures is crucial. Complementary FET (CFET) technology offers dramatic improvement in memory and standard cell densities through vertical stacking of nFET and pFET devices. In addition to area efficiency, CFETs enjoy competitive performance at the sub- 3 nm technology node. This work presents a comprehensive performance and aging analysis of a CFET-based 6T-SRAM array, including a comparison with the Nanosheet FET (NSFET) technology. A 32-bit SRAM memory array, including read and write peripheral circuits, is simulated for both technologies. To carry out the SRAM SPICE simulations, accurately calibrated industry-standard BSIM-CMG models are deployed. The SRAM assessment includes noise margins, access delays, and energy consumption. Our investigations reveal that CFET technology offers substantial reductions in access times and energy consumption compared to NSFET. Finally, the impact of aging on different performance metrics is presented for the CFET-based SRAM design.
CMOS scaling is now entering a challenging phase due to issues with lithography and device physics. Heterogeneous 3D integration technology is a costeffective and highperformance alternative to planar integrated circuits (ICs). In this paper, we propose an onchip power distribution network (PDN) model for heterogeneous 3DICs (H3DlCs), w hich explicitly takes the effects of on chip inductance into account. With this model, we can perform both transient and AC simulations efficiently. As the inductive effect is included in our model, it can also provide a precise assessment of the noise characteristics of H3DICs at elevated frequencies and can better answer "whatiF' type questions for design space exploration in the early PDN design stage. The model is validated through HSPICE, demonstrating a maximum error of less than 1%. It also shows an average increase of 1.5x in transient simulation speed and an average enhancement of 8.Sx in AC simulation speed. The paper also investigates the effects of die stacking order and through silicon via (TSV) count on power supply noise (PSN) in H3DICs. With the proposed model, the impacts of die stacking order and TSV density on PSN can be evaluated effectively and efficiently.
Demand for latency sensitive computing is driving the need to push computing resources closer to the source of data leading to the spurt in the growth of 'clusters at the edge'. However, edge devices are severely constrained with the availability of computing resources, power etc. especially when the need is to setup an edge cluster in an unfamiliar or a hostile environment. This problem can be solved by adding the available dynamic edge devices or host into the edge cluster for a specific period of time, share a fraction of their computing resources and leave the cluster at will. Addition of the dynamic host into the edge cluster using a mutual trust based agreement form a hybrid edge cluster. This hybrid architecture not only helps to enhance the throughput of the edge cluster but also reduces the job execution cost as incorporation of 'opportunistically available dynamic hosts' comes at 0-cost. Most of these 'dynamic hosts' work on a synergistic partnership model - the same dynamic node can be 'source' and 'sink' of these "latency sensitive tasks". Proper allocation of the job within the hybrid edge cluster is also very important parameter to enhance the execution efficiency of the job within the cluster. In this work, a novel architecture of such a hybrid edge cluster consisting of both static and dynamic host is proposed along with proper job scheduling algorithm to reduce the job execution latency of the cluster and job execution costs. The efficiency of the proposed architecture and scheduling algorithm has been compared with the state of the art solutions in terms of job execution cost, latency and cluster throughput.
In sensory networks, large amounts of raw data are locally captured by sensor terminals but remain unprocessed. While such analog sensory data can be processed using (lightweight) digital processing solutions (e.g., in-memory computing) at the edge devices, the need for signal-domain conversions (i.e., analog to digital), necessary for storing and processing the data, imposes high power and area consumption, limiting the computational capacity at the edge. In this invited paper, we discuss the promise of photonic in-memory computing, based on phase change material integrated with silicon photonic devices, as an analog computing solution to process the sensory data at the edge without the need for power-hungry signal conversions.
Flexible Electronics (FE) technology offers uniquecharacteristics in electronic manufacturing, providing ultra-low-cost, lightweight, and environmentally-friendly alternatives totraditional rigid electronics. These characteristics enable a rangeof applications that were previously constrained by the costand rigidity of conventional silicon technology. Machine learning (ML) is essential for enabling autonomous, real-time intelligenceon devices with smart sensing capabilities in everyday objects. However, the large feature sizes and high power consumption ofthe devices oppose a challenge in the realization of flexible ML applications. To address the above, we propose an open-source framework for developing ML co-processors for the Bendable RISC-V core. In addition, we present a custom ML accelerator architecture for Support Vector Machine (SVM), supporting both one-vs-one (OvO) and one-vs-rest (OvR) algorithms. Our ML accelerator adopts a generic, precision-scalable design, supporting 4-, 8-, and 16-bit weight representations. Experimental results demonstrate a 21x improvement in both inference execution time and energy efficiency, on average, highlighting its potential for low-power, flexible intelligence on the edge.
The prevalence of Artificial Intelligence (AI) applications has been undisputed in most fields of modern computing. As the paradigm shifts from high-performance Cloud computing infrastructure to decentralized smart Edge devices that offer higher reliability and lower latency, with no need for high-speed connectivity, more effort has been required to address resource and energy concerns. In this paper, we present the advancements of the HORIZON EU CONVOLVE project and focus on the development of flexible accelerators targeting several types of modern Edge AI applications. We outline the architectural decisions for the CONVOLVE SoC and highlight the various techniques employed in 4 of our developed accelerators. These steps mark a significant step toward enabling Ultra-Low Power (ULP) AI processing at the edge. Finally, we present quantitative hardware results and discuss the design trade-offs and performance characteristics of the proposed micro-architectures.
The integration of AI with edge computing and IoT is transforming smart systems by enabling real-time decision making, improving data privacy, and optimizing resource efficiency. Edge AI addresses key challenges of traditional cloud-centric models, but faces strict limitations on compute power, memory, energy, communication bandwidth, security, energy consumption, and scalability. To address this strict limitation, various techniques have been developed to create energyefficient, secure, lightweight AI architectures. This article presents a comprehensive review of secure and sustainable Edge AI technologies that highlight recent advances in the design, optimization, and security of AI models for such environments. We discuss model compression (pruning, quantization, and knowledge distillation) and lightweight architectures (e.g., MobileNet, TinyML frameworks)and cross-layer optimization to enhance edge AI efficiency. It also addresses security and privacy concerns such as adversarial attacks, model theft, and side-channel vulnerabilities including solutions such as secure boot, trusted execution environments (TEEs), adaptive model switching, and privacy-preserving techniques such as federated learning and differential privacy. We highlight critical challenges, analyze ongoing research trends, and outline future research directions essential to building secure, energy efficient, and intelligent edge ecosystems.
A bistable superconducting quantum interference device (SQUID) exclusively comprising Josephson junctions (JJs) is proposed. The design integrates two 2 Phi-JJs within the loop structure, while the state of the SQUID is monitored through a conventional 2 pi-periodic JJ (0-JJ). This configuration eliminates the need for geometric inductors, leveraging the nonlinear phase dynamics for bistability. Extensive simulations confirm robust bistable operation under controlled external flux bias, positioning the proposed SQUID as an area-efficient building block for superconducting memory cells, sensors for various applications, and SFQ-compatible logic elements.
With continuous transistor scaling in nanoscale technology nodes, predicting device performance and analyzing reliability have become increasingly challenging. Technology Computer-Aided Design (TCAD) tools offer detailed physical modeling with atomistic-level accuracy without costly prototyping or wafer-level measurements. However, creating TCAD device files remains labor-intensive and requires domain expertise. Recent advances in large language models (LLMs) offer promising opportunities to automate stages of electronic design automation (EDA). While LLMs have shown promise in other EDA domains, their application to TCAD simulation remains underexplored. This work presents ChatTCAD, a framework that fine-tunes an LLM to automatically generate TCAD device files from natural language descriptions. Our approach combines a synthetically constructed dataset with carefully designed prompt strategies to support both single-function and complete-device script generation. Experimental results show that ChatTCAD can generate high-quality, executable TCAD device files.
In post-CMOS technology era, emerging data structures for logic synthesis and technology mapping have gained importance to support efficient design automation. Majority-Inverter Graph (MIG) comprise a homogeneous structure of majority and inverter nodes and has recently emerged as a prominent logic representation structure for logic synthesis and optimization. Minority-majority-inverter graph (mMIG), which comprises of majority, minority and inverter node, shows a promise in optimizing inverter count, power, and the critical delay. In this work, we improve the existing mMIG framework by refining and introducing optimized transformation rules including associativity, distributivity, swapping reconvergence, swapping non-reconvergence, relevance, and substitution for circuits with minority nodes. With mMIG-based implementations of Addition-Rotation-XOR (ARX) boxes, namely MARX-2 and SPECKEY, along with ISCAS-85 multiplier and adder circuits, we demonstrate the reduction in number of gates, inverter count, power usage, and critical delay when compared to MIG and AND-OR-inverter graph (AOIG) synthesized circuits. Our results demonstrate circuits based on mMIG achieve upto 30 to 40% reduction in gate count, in some cases the complete elimination of inverters, 20% on-chip power savings, and around 10% delay optimization over MIG and AOIG synthesis in certain typical circuits.
Edge computing applications, such as IoT and wearable devices, demand energy-efficient and high-performance hardware accelerators to support neural networks in resource-constrained environments. This paper presents a novel Multiply-Accumulate (MAC) unit based on Most Significant Digit First (MSDF) arithmetic, designed to address these challenges. The proposed MSDF MAC unit exploits digit-level parallelism and eliminates carry propagation delays to enhance throughput and reduce energy consumption. We integrate this unit into three different widely used applications: (I) Sparse Matrix-Vector Multiplication (SpMV), (II) Multi-Layer Perceptron (MLP), and (III) Denoising Autoencoder. All designs are synthesized using TSMC 45nm CMOS technology, and the proposed designs achieve significant improvements, including 1.69x speedup and up to 60.4% energy reduction on SpMV, and at least 39% power savings on MLP with maintained accuracy for the MLP and the autoencoder. These results demonstrate the potential of MSDF-based accelerators for efficient neural network deployment on edge devices.
This paper presents a novel authentication platform for IoT devices in wireless communication systems, leveraging physical-layer characteristics and Physical Unclonable Functions (PUFs) to enable secure, lightweight, and device-specific authentication. The proposed platform is made up of three main components: a frequency generation unit, a modulator unit, and a real-time demodulator/frequency detection. The first two components, embedded in the IoT module, generate unique carrier signals based on process variations ensuring that each device utilizes a distinct frequency set for data modulation. The frequency selection is made with a PUF response in order to be unpredictable by an attacker. The final component, a realtime demodulator and frequency counter in the master module, enables continuous authentication, verifying the legitimacy of the transmitting IoT module both at initialization and throughout communication in real-time.
This is an overview of Intracom Telecom’s research activities within the context of Horizon 2020 and Horizon Europe research and innovation frameworks. Results from projects ARIADNE and TERRAMETA will be presented, showcasing the development of beyond 5G systems and towards 6G technologies at the THz frequencies domain.
3D face reconstruction is a hot topic in computer graphics and vision, with many efficient algorithms recently proposed that offer good performance but suffer from high computational complexity. The FaceScape algorithm is promising, integrating prior knowledge to effectively recover highly detailed and riggable 3D face models from a single image input with high robustness. Its computations are relatively small but still cannot meet real-time requirements in most application scenarios. In this paper, we propose a high-speed hardware accelerator for the core part (namely the Limited-memory Broyden-Fletcher-Goldfarb-Shanno (L-BFGS) algorithm) of FaceScape aiming to deal with this problem. Many optimization techniques, especially novel algorithmic transformations and architectural schemes, have been introduced and applied. Experimental results demonstrate that our FPGA implementation of L-BFGS for FaceScape achieves approximately 5.6x speedup over the optimized C implementation and runs over 100x faster than the original Python implementation.
