Three-dimensional (3D) heterogeneous integration of InP and SiC substrates is a promising technology for realizing high-performance RF and millimeter-wave (mmW) systems. In this work, we demonstrate a robust through-InP-via (TIV)-embedded 3D integration platform between InP to SiC enabling vertical signal routing directly to the topmost surface. Unlike previous studies limited to lateral signal extraction, this study successfully implements a vertical interconnection using a cost-effective process based on standard microfabrication equipment. To address thermal budget mismatches observed in conventional solder bonding, we optimized the process by adopting Au-Sn eutectic bonding. After the upper InP layer was thinned from 630 mu m to 5 mu m to form TIV, we apply a low-temperature photo-definable dielectric, effectively eliminating delamination issues. Subsequently, metal filling was formed on the TIV holes through selective wet etching and electroplating processes. A coplanar waveguide (CPW) integrated into the proposed structure exhibited a favorable insertion loss of 1.21 dB/mm at 30 GHz. This result represents the experimental validation of RF characteristics measured directly from the top-surface pads of a TIV-embedded InP-to-SiC stack, confirming its potential for next-generation mmW modules.

Edge computing devices, which generate, collect, process, and analyze data near the source, enhance the data processing efficiency and improve the responsiveness in real-time applications or unstable network environments. To be utilized in wearable and skin-attached electronics, these edge devices must be compact, energy efficient for use in low-power environments, and fabricable on soft substrates. Here, we propose a flexible memristive dot product engine (f-MDPE) designed for edge use and demonstrate its feasibility in a real-time electrocardiogram (ECG) monitoring system. The f-MDPE comprises a 32×32 crossbar array embodying a low-temperature processed self-rectifying charge trap memristor on a flexible polyimide substrate and exhibits high uniformity and robust electrical and mechanical stability even under 5-mm bending conditions. Then, we design a neural network training algorithm through hardware-aware approaches and conduct real-time edge ECG diagnosis. This approach achieved an ECG classification accuracy of 93.5%, while consuming only 0.3% of the energy compared to digital approaches. Furthermore, our simulations indicated that the energy reduction could be further reduced to 0.001% through device scaling to a 100-nm-line width, highlighting the strong potential of this approach for emerging edge neuromorphic hardware.

Next-generation wireless communication systems, such as 6G, require high-frequency, multifunctional, and power-efficient systems. A promising solution is the heterogeneous and monolithic 3D (HM3D) integration of III-V technology for RF functions and CMOS technology for analog and digitalfunctions on the same chip. Despite extensive research on HM3D integration of III-V on Si CMOS, implementations have been limited to the RF device level. In this work, we present and demonstrate HM3D integrated RF amplifiers utilizing top-tier InGaAs HEMTs and CMOS-based backside integrated passive devices (BS-IPDs). We achieved fT and fMAX of 609 and 455 GHz utilizing HM3D integrated top-tier 65-nm-gate InGaAs HEMTs, which is record-high RF performance among M3D transistors. The BS-IPDs show stable and consistent behavior, maintaining the same characteristics before and after HM3D integration due to the low-temperature wafer bonding process. Ultimately, HM3D RF integrated amplifiers based on developed HM3D integrated top-tier InGaAs HEMTs and BS-IPDs technologies exhibit a high gain of 15.6 dB at 31 GHz, the first demonstration of an HM3D RF circuits and the highest gain among M3D RF circuits. These results represent a significant milestone in advancing from device-level to circuit-level research, paving the way for complete HM3D RF systems in next-generation wireless communication.

In this article, we prove that small localized data yield solutions to Kawahara-type equations which have linear dispersive decay on a finite time scale depending on the size of the initial data. We use the similar method used by Ifrim and Tataru to derive the dispersive decay bound of the solutions to the KdV equation, with some steps being simpler. This result is expected to be the first result of the small data global bounds of the fifth-order dispersive equations with quadratic nonlinearity.

In this article, we prove that small localized data yield solutions to Higher order Korteweg-de Vries type equation with scattering-supercritical nonlinearity have linear dispersive decay in only a finite length of time. The proof is done by using space-time resonance method and analyzing the oscillatory integrals on the Fourier side.

In this study, we demonstrated a silicon (Si)-based integrated passive device (IPD) stack to support III-V/Si monolithic 3D (M3D) ICs operating on the radio frequency (RF) band. The IPD stack was fabricated based on an 8-inch CMOS process line and integrated via M3D with an InGaAs HEMT layer. A process condition for a trap rich layer and a buried oxide layer in the IPD was established to simultaneously minimizing both the RF loss and wafer bowing. Through the process condition, the RF loss of the coplanar waveguides was -0.631 dB/mm at 30 GHz, lower than that of the CMOS foundry, and the wafer bowing of the stack was as low as -5.5 mu m. The maximum quality factor of the inductors showed good values when compared to those of other CMOS foundry process-based inductors operating on the RF bands reported thus far. To obtain a compressive profile for the IPD stack, which is one of the most important requirements in advancing to wafer-to-wafer-level 3D bonding with the III-V active layer, a process method for the final IMD layer of the IPD was developed, resulting in a change from a tensile profile to a compressive profile for the IPD (corresponding wafer bowing value from -12.6 to + 10.7 mu m).

Heterogeneous and monolithic 3D (HM3D) integration of III-V and Si CMOS technologies enables high-frequency, multifunctionality, and power-efficient RF systems for next-generation wireless communication such as 6G and beyond. In this work, for the first time, we demonstrate HM3D integration of InGaAs HEMTs (for LNAs) and InP/InGaAs DHBTs (for PAs) on Si CMOS by direct wafer bonding. The top InGaAs HEMTs exhibit $f_{\mathrm{T}}$ and $f_{\text{MAX}}$ of 354 GHz and 611 GHz with a high $g_{\mathrm{m}}$ of 1.5 S/mm. Concurrently, the top InP/InGaAs DHBTs show $f_{\mathrm{T}}$ and $f_{\text{MAX}}$ of 129 GHz and 47 GHz with a DC gain of 29 and a breakdown voltage of 5.9V. Notably, these results are obtained without any degradation of the bottom Si CMOS. This innovative HM3D integration, combining III-V technologies for PAs and LNAs with Si CMOS technology for analog/digital functionalities will play an essential role in next-generation wireless communication systems.

Flip-chip microbump (μ-bump) bonding technology between indium phosphide (InP) and silicon carbide (SiC) substrates for a millimeter-wave (mmW) wireless communication application is demonstrated. The proposed process of flip-chip μ-bump bonding to achieve high-yield performance utilizes a SiO2-based dielectric passivation process, a sputtering-based pad metallization process, an electroplating (EP) bump process enabling a flat-top μ-bump shape, a dicing process without the peeling of the dielectric layer, and a SnAg-to-Au solder bonding process. By using the bonding process, 10 mm long InP-to-SiC coplanar waveguide (CPW) lines with 10 daisy chains interconnected with a hundred μ-bumps are fabricated. All twelve InP-to-SiC CPW lines placed on two samples, one of which has an area of approximately 11 × 10 mm2, show uniform performance with insertion loss deviation within ±10% along with an average insertion loss of 0.25 dB/mm, while achieving return losses of more than 15 dB at a frequency of 30 GHz, which are comparable to insertion loss values of previously reported conventional CPW lines. In addition, an InP-to-SiC resonant tunneling diode device is fabricated for the first time and its DC and RF characteristics are investigated.

A terahertz (THz) fundamental oscillator IC with high efficiency and compact chip size based on an indium phosphide (InP)-based resonant tunneling diode (RTD) is proposed. The oscillator is designed by utilizing a low-frequency bias stabilizer, along with utilizing a negative differential resistance oscillator topology. The oscillator is fabricated by using an InP monolithic THz integrated circuit multilayer process. The fabricated oscillator shows a high dc-to-RF power efficiency ( η ) of 0.274 % with a low dc power consumption of 3.4 mW and an RF output power of 9.3 μ W at an oscillation frequency of 692 GHz. The IC exhibits a chip size of 300 × 380 μ m 2 excluding the measurement pads. The achieved η and chip size are good values among THz oscillators above 500 GHz reported to date.

This is the first demonstration of sidewall slope control of InP via holes with an etch depth of more than 10 μm for 3D integration. The process for the InP via holes utilizes a common SiO2 layer as an InP etch mask and conventional inductively coupled plasma (ICP) etcher operated at room temperature and simple gas mixtures of Cl2/Ar for InP dry etch. Sidewall slope of InP via holes is controlled within the range of 80 to 90 degrees by changing the ICP power in the ICP etcher and adopting a dry-etched SiO2 layer with a sidewall slope of 70 degrees. Furthermore, the sidewall slope control of the InP via holes in a wide range of 36 to 69 degrees is possible by changing the RF power in the etcher and introducing a wet-etched SiO2 layer with a small sidewall slope of 2 degrees; this wide slope control is due to the change of InP-to-SiO2 selectivity with RF power.

In this article, an improved layout design and a base-collector undercut etching process have been proposed and demonstrated for a high-speed InP/InGaAs heterojunction bipolar transistor (HBT). The fabricated HBT using proposed methods has a smaller parasitic base-collector (B-C) area, resulting in reduced B-C capacitance (C-BC), a reduction of 36% compared to that in the conventional HBT. A current gain cutoff frequency (f(T)) and a maximum oscillation frequency (f(max)) of the proposed HBT have been increased from 110 to 131 GHz and from 112 to 131 GHz due to the reduced C-BC. These results clearly show the effectiveness of the proposed technique for the HBTs.

In this letter, we propose an area-efficient series-connected resonant tunneling diode pair device (SCRTD) to utilize as a binary neuron device in cellular neural networks (CNNs). The proposed SCRTD (P-SCRTD) consists of two RTDs interconnected by a floating metal layer with a high-doped epitaxial layer. The P-SCRTD shows a 48 % reduction in area by eliminating the isolation area in the conventional SCRTD (C-SCRTD) owing to the symmetrical I-V characteristic of the RTD, without any performance penalty on the DC and RF characteristics by means of adopting the floating metal layer, compared to the C-SCRTD. CNN application of the P-SCRTD is investigated, showing inherent threshold operation and high-speed (12.5 Gbps) low-power (21 mW) performance, despite using the 2 μm technology node, for a unit cell for edge extraction.

This study reports an analysis of noise figures (NFs) in a reflection-type microwave amplifier using resonant tunnelling diodes (RTDs). The minimum NF for the RTD amplifier based on 0.9 mu m InP process technology, featuring a power gain (S-21) of 10.4 dB and a dc-power consumption of 133 mu W at a centre frequency of 5.7 GHz, is measured to be 5.08 dB at a bias voltage of 0.355 V. The estimated NF characteristic based on an equation of the noise factor caused by the shot noise (F-SH) and a simulation of the noise factor generated by the thermal noise (F-TH) closely matches the measured NF characteristic, in the high-gain bias range of 0.32-0.38 V and near the centre frequency. It is found that the measured NF value of 5.08 dB originates mostly from the F-SH of 1.88 and the F-TH of 2.02. Additionally, the effect of the RTD parameters on the achieved NF is investigated, indicating that the negative resistance (R-D) magnitude had a dominant effect on the NF by changing the F-TH as well as the F-SH.

This paper presents a low-noise reconfigurable sensor readout circuit with a multimodal sensing chain for voltage/current/resistive/capacitive microsensors such that it can interface with a voltage, current, resistive, or capacitive microsensor, and can be reconfigured for a specific sensor application. The multimodal sensor readout circuit consists of a reconfigurable amplifier, programmable gain amplifier (PGA), low-pass filter (LPF), and analog-to-digital converter (ADC). A chopper stabilization technique was implemented in a multi-path operational amplifier to mitigate 1/f noise and offsets. The 1/f noise and offsets were up-converted by a chopper circuit and caused an output ripple. An AC-coupled ripple rejection loop (RRL) was implemented to reduce the output ripple caused by the chopper. When the amplifier was operated in the discrete-time mode, for example, the capacitive-sensing mode, a correlated double sampling (CDS) scheme reduced the low-frequency noise. The readout circuit was designed to use the 0.18-µm complementary metal-oxide-semiconductor (CMOS) process with an active area of 9.61 mm2. The total power consumption was 2.552 mW with a 1.8-V supply voltage. The measured input referred noise in the voltage-sensing mode was 5.25 µVrms from 1 Hz to 200 Hz.

This study reports on a sub-mW triple-push oscillator using resonant tunnelling diodes (RTDs) operating at a frequency of 225 GHz. The triple-push RTD oscillator is designed based on a stability test using even/odd-mode equivalent circuit models and fabricated by using an indium phosphide monolithic microwave integrated circuit process. The fabricated IC exhibits an extremely low dc-power consumption (P-DC) of 0.5 mW with a dc-to-radio-frequency efficiency of 1%. These results are attributed to both device characteristics of the RTDs with a low bias voltage of 0.4 V and a low peak current density of 0.74 mA/mu m(2) and an efficient triple-push topology exploiting the strong odd symmetry of the RTD I-V curve with a wide negative differential conductance voltage span of 0.46 V.

A reflection-type microwave amplifier using InP-based resonant tunnelling diodes (RTDs) has been designed and fabricated. The implemented amplifier shows a low dc-power consumption of 270 μW with RF gains of more than 11 dB at 5.61 GHz. Temperature-dependent characteristics of the RTD amplifier have been investigated at a high temperature. With increasing temperature from 25 to 100°C, the centre frequency shift was measured to be 60 MHz. The RF gains (S21/S12) and the return losses (S11/S22) of the amplifier decreased from 11.45/11.32 and −7.96/−8.11 dB at 25°C to 7.06/6.91 and −11.36/−11.15 dB at 100°C, respectively. The S-parameter degradation phenomena are shown to mainly arise from the temperature dependence of the negative differential resistance (RD) characteristic for the fabricated RTD.

This letter presents a resonant tunneling diode (RTD)-based differential oscillator topology which can enhance output power coupling for THz applications. In order to combine the differential output signals of the RTD differential oscillator, an on-chip dipole antenna is integrated into the InP-based RTD monolithic microwave integrated circuit technology. The fabricated RTD differential oscillator shows a radiated output power of 47 μW with a total dc power consumption of 14.1 mW at an oscillation frequency of 675 GHz. A high dc-to-RF efficiency of 0.33% has been obtained. This is the first implementation as an RTD differential oscillator topology for THz sources, integrated with the on-chip dipole antenna.

This letter reports the analysis of RF power characteristics in a microwave amplifier using resonant tunneling diodes (RTDs). The implemented IC shows a return loss of more than 11 dB with a low dc-power consumption of 0.42 mW and a power gain of 8.6 dB at 5.8 GHz. The maximum linear RF output power with a uniform gain of 8.6 dB is measured to be -25.4 dBm at the same frequency. The gain hump phenomenon is observed in an input power range from -32 dBm to -16 dBm, and is shown to arise from a sudden movement of the operating point from the negative differential resistance (NDR) region to the positive differential resistance (PDR) region, based on a large-signal load-line analysis together with a harmonic balance simulation.