Semiconductor Quantum Dots (QDs) have invoked a high interest in the industrial optoelectronic applications due to their high photogeneration ability compared with Silicon materials, in addition to the ease of adjusting them to interact with specific wavelengths by controlling the QD size, whether as a light emitter such as screens or as a light receiver such as imaging applications. We investigate the reliability performance of an optimized (PbS) Quantum Film (QF) based photodiode, and we demonstrate that AC operations drastically improve the reliability performance of QD-based photodiodes.

Quantum dot photodetectors are a promising platform technology that ST Microelectronics has developed, scaled‐up, and is ready to commercialize. Our quantum dot‐based global shutter imagers are responsive from UV to SWIR wavelengths at high resolution, high efficiency, and low dark currents, with good reliability and very competitive cost. Sampling to customers is now ready to start.

In this work, we demonstrate the powerful methodology of electronic transport characterization in highly scaled (down to 14nm-node) FDSOI CMOS devices using cryogenic operation under interface coupling measurement condition. Thanks to this approach, the underlying scattering mechanisms were revealed in terms of their origin and diffusion center location. At first we study quantitatively transport behavior induced by the high-k/metal gate stack in long channel case, and then we investigate the transport properties evolution in highly scaled devices. Mobility degradation in short devices is shown to stem from additional scattering mechanisms, unlike long channel devices, which are attributed to process-induced defects near source and drain region. Especially in PMOS devices, channel-material related defects which could be denser close to front interface also induce mobility degradation.

A thorough investigation and statistical analysis of the low-frequency (LFN) and random telegraph noise (RTN) in 28 and 14nm FD-SOI CMOS transistors is presented, for the first time. It is shown that the 14nm technology node is improved in terms of threshold voltage fluctuations when compared to the 28nm one. A new analysis method that directly probes the RTN presence is also proposed. Finally, the LFN/RTN impact on the device dynamic variability is presented through CADENCE design suite circuit simulations.

The feasibility of geometric magnetoresistance (MR) measurement from linear to saturation operation regime is demonstrated in ultrathin body and BOX fully depleted silicon-on-insulator devices from 14-nm technology node. Besides, we propose a new physical compact model for MOSFET drain current under high field transport, which reproduces experimental MR mobility from linear to saturation operation region and serves as the basis for a new extraction method of carrier saturation velocity. A benchmarking with state-of-the-art saturation velocity extraction methodologies is also conducted. Our saturation velocity results indicate that, for this technology, nonstationary transport prevails as manifested by an overshoot velocity behavior, still far from the ballistic limit.

In this paper, carrier transport properties in highly scaled (down to 14nm-node) FDSOI CMOS devices are presented from 77K to 300K. At first, we analyzed electron transport characteristics in terms of different gate-oxide stack in NMOS long devices. So, we found that SOP and RCS can be the dominant contribution of additional mobility scatterings in different temperature regions. Then, electron mobility degradation in short channel devices was deeply investigated. It can be stemmed from additional scattering mechanisms, which were attributed to process-induced defects near source and drain. Finally, we found that mobility enhancement by replacing Si to SiGe channel in PMOS devices was validated and this feature was not effective anymore in sub-100nm devices. The critical lengths were around 50nm and 100nm for NMOS and PMOS devices, respectively.

As CMOS technology scales down, two paths are pursued by the industry to overcome the fundamental limits of traditional planar bulk transistors. One is the introduction of a Tri-Gate or FinFET transistor at the 22 and 16 nm nodes [1, 2]. These architectures provide impressive drive currents per footprint at low supply voltages because of the 3-D conduction channel and excellent electrostatic control. Conversely, they have high gate and parasitic capacitances, proportional to the 3-D effective W increase, which negatively impacts both the speed and active power consumption. Alternatively FDSOI provides an evolutionary path. First introduced at the 28nm node [3], FDSOI includes excellent mismatch properties, a simplified planar manufacturing process vs 3-D finFET technology and capitalization of existing design techniques. It also extends the possibility of back biasing and therefore offers unique “smart” solutions for dynamic power optimization [4]. The technology presented in this paper furthers the appeal of FDSOI to the 14nm node [5]. Compared to the 28nm technology, new Front-End process elements include a dual SOI/SiGeOI N/P channel, a dual workfunction gate-first HKMG integration scheme and a dual in-situ doped Si:CP/SiGeB N/P raised source-drain [5]. Additionally hybrid bulk areas, formed before Shallow Trench Isolation (STI), provide a space for passive devices and ESD FETs to be built [6]. The strained-SiGe channel (cSiGe) is realized before STI patterning to avoid SiGeOI over-thinning linked to the Ge condensation process at active edges [7] (Fig.1). As shown in Fig.1, strain into the channel has been experimentally measured by Nano-Beam Electron Diffraction (NBED) : 1% compressive strain in the 6nm thin SiGeOI channel (25%Ge) is demonstrated. After gate patterning, a N/P dual spacer/dual epitaxy scheme is used, as illustrated in Fig.2.Since gate-to-drain capacitance (Cgd) is of high importance for the circuit speed and power, spacer, poly thickness and raised source-drain epitaxy (Fig.2) has been optimised to minimize Cgd down to ~0.3fF/µm for both n and pMOS devices. cSiGe and SiGeB source-drain implementation in 14nm FDSOI provides a large pMOS drive current enhancement when compared to FDSOI technology at the 28nm node. As a result of low Cgd and large pMOS drive current, 14FDSOI technology demonstrated in [5] a -20% delay gain with the Fan-Out 3 (FO3) RO inverters at the same static leakage and a 100mV Vdd reduction (0.8V vs 0.9V) over the 28nm FDSOI technology (Fig.3). From this previous work, the transistor performance has further progressed and the delay boost is now established at -34% with -100mV Vdd operation, as shown in Fig.3. It means >50% speed frequency in 14FDSOI at 0.8V Vdd vs 28FDSOI at 0.9V Vdd. These large performance enhancements over 28FDSOI make 14FDSOI as a leading edge technology for the 14nm node and a highly competitive technology for low voltage and energy efficient CMOS applications. References: [1] C.-H. Jan et al., IEDM Tech. Dig., 2012, [2] S.-Y. Wu et al., IEDM Tech. Dig., 2013, [3] N. Planes et al., VLSI Symposium Tech. Dig., 2012, [4] F. Arnaud et al., IEDM Tech. Dig., 2012, [5] O. Weber et al., VLSI Symposium Tech. Dig., 2014, [6] D. Golanski et al., VLSI Symposium Tech. Dig., 2013, [7] K. Cheng et al., IEDM Tech. Dig., 2012. Figure 1

The feasibility of full split C-V method in ultra-thin body and BOX (UTBB) FDSOI devices is demonstrated, emphasizing the usefulness of gate-to-bulk capacitance. The split C-V measurements carried out on both gate-to-channel and gate-to-bulk mode are shown to be consistent with TCAD simulation. This enabled us to propose an improved parameter extraction methodology for the whole vertical FDSOI stack from gate to substrate using back biasing effect. (C) 2014 Elsevier Ltd. All rights reserved.

Modeling local electrical fluctuations on pocket transistor is a challenging task, especially for relatively long gate transistors. Previous work highlighted and qualitatively explain the anomalously high random dopant induced increase of local fluctuations in rather long and heavily pocket device but could not accurately provide the amplitude of the phenomenon. In this paper, a new physical mismatch model is introduced. It is based on the three-transistor model, where one transistor is used to model the channel region and the other two for the pocket regions. This mismatch model provides both qualitative and quantitative mismatch results for all transistor gate lengths and furthermore, it is valid from weak to strong inversion regimes. After the model presentation, a detailed discussion of the qualitative results is performed. Afterwards, the experimental setup is presented. Finally, the physical parameters of the model are characterized and then the resulting level of fluctuations is shown to well model the experimental results.

In this study, a new technique to extract the S/D series resistance (R-sd) from the total resistance versus transconductance gain plot R-tot(1/beta) is proposed. The technique only requires the measurement of I-d(V-gs)vertical bar(Vgt) and beta, allowing fast and statistical analysis in an industrial context. Unlike the usual R-tot(L)-based techniques, it has the advantage of being insensitive to the channel length and mobility variations and finally enables to extract very accurate values for R-sd(V-gs) and the effective mobility reduction factor mu(eff)(V-gt)/mu(eff)(0).

Pocket architecture is a useful technique to eliminate short channel effects. However, it has been shown an influence on mismatch performances. In this paper, different implant trials are done on NMOS devices with dose and energy variation. For the first time, the impact of indium implant will be analyzed to optimize mismatch performance. It is demonstrated that this implant decreases significantly the mismatch. Moreover, it diminishes the variability not only at small gate lengths but also at large ones.