The successful integration of capacitive phase shifters featuring a p-type strained SiGe layer in a 300 mm silicon photonics platform is presented. The phase shift is evaluated with a voltage swing of only 0.9 Vpp, compatible with CMOS technology. A good correlation is shown between the phase shift efficiency from 10 to 60°/mm and the capacitive oxide thickness varying from 15 to 4 nm. Corresponding insertion losses are as low as 3 dB/mm thanks to the development of low loss poly-silicon and to a careful design of the doped layers within the waveguide. The thin SiGe layer brings an additional 20% gain in efficiency due to higher hole efficiency in strained SiGe.

In this work, heated implantation impact on defect generation is observed for non-amorphizing conditions and specific anneal. Photoluminescence imaging method has been used and exhibits radiative defect density variation with chuck temperature. Moreover, to understand the behavior of such implantation in terms of defect generation and depth profile, effectiveness of Kinetic Monte Carlo (KMC) simulations is discussed.

In this paper, we present an enhanced differential Hall effect measurement method (DHE) for ultrathin Si and SiGe layers for the investigation of dopant activation in the surface region with sub-nanometre resolution. In the case of SiGe, which constitutes the most challenging process, we show the reliability of the SC1 chemical solution (NH4OH/H2O2/H2O) with its slow etch rate, stoichiometry conservation and low roughness generation. The reliability of a complete DHE procedure, with an etching step as small as 0.5 nm, is demonstrated on a dedicated 20 nm thick SiGe test structure fabricated by CVD and uniformly doped in situ during growth. The developed method is finally applied to the investigation of dopant activation achieved by advanced annealing methods (including millisecond and nanosecond laser annealing) in two material systems: 6 nm thick SiGeOI and 11 nm thick SOI. In both cases, DHE is shown to be a uniquely sensitive characterisation technique for a detailed investigation of dopant activation in ultrashallow layers, providing sub-nanometre resolution for both dopant concentration and carrier mobility depth profiles.

Optical properties of poly-silicon material are investigated to be integrated in new silicon photonics devices, such as capacitive modulators. Test structure fabrication is done on 300 mm wafer using LPCVD deposition: 300 nm thick amorphous silicon layers are deposited on thermal oxide, followed by solid phase crystallization anneal. Rib waveguides are fabricated and optical propagation losses measured at 1.31 µm. Physical analysis (TEM ASTAR, AFM and SIMS) are used to assess the origin of losses. Optimal deposition and annealing conditions have been defined, resulting in 400 nm-wide rib waveguides with only 9.2-10 dB/cm losses.

The authors have measured and compared the stress in nickel silicide full sheet layers prepared with added platinum on (001) p-type Si wafers by using either a rapid thermal anneal (RTA) at 390 °C or a millisecond submelt laser dynamic scanning anneal (DSA) at 800 °C. The room temperature tensile stress of the silicide annealed with DSA is 1.65 GPa, whereas that of the silicide annealed with RTA at 390 °C is 800 MPa. Our analysis confirms that the origin of the stress lies in thermal expansion factors. Despite some small variations, the stress remains highly tensile in both layers after a 1 h post-treatment at 400 °C, with values of 1.4 GPa and 850 MPa for the DSA and RTA samples, respectively. The authors also performed strain measurements with dark field electron holography in the source drain region of 28 nm field complementary metal oxide semiconductor field effect transistors, under the silicide dot. They then determined the stress inside the silicide by combining the strain measurement with finite element mechanical simulations; values of 1.5 GPa and 600 MPa were found at the nanometer scale for the DSA and RTA samples, respectively, which are consistent with the macroscopic observations.

A comparison of mechanical properties of amorphous silicon nitride thin films deposited with various techniques used for microelectronic applications was conducted. Nitride films with thicknesses less than 80nm were deposited on (001) oriented silicon wafers by using various methods: low pressure chemical vapor deposition (LPCVD), rapid thermal CVD (RTCVD), atomic layer deposition (ALD) and plasma enhanced CVD (PECVD). The wafer curvature method was used to show that the as-deposited LPCVD, RTCVD and ALD films exhibited tensile residual stresses that decreased with silicon richness. In contrast, the stress of the PECVD as-deposited layers ranged from tensile to ultra-compressive, depending on the exposure to high plasma power and ion bombardment during growth. After high temperature annealing, the LPCVD, RTCVD and ALD nitride stresses were almost unchanged, indicating that these films/substrate systems have significant thermal mechanical stability. In contrast, it was observed that, regardless of the initial stress, the annealed PECVD films developed tensile stress after high temperature treatment, with the same dependence of stress on refractive index as was found with the other deposition techniques. The Young's moduli, measured by performing nano-indentation on 200nm thick nitride layers, were found for most samples to be correlated with film density.

Back surface passivation is one of the major challenges in the backside illuminated sensor technology. Ion implantation followed by non-melt pulsed Laser Thermal Annealing (LTA) has been identified as a promising candidate to address this issue. In this work, a shallow B-doped layer is implanted at the backside, further activated using LTA in the non-melt regime. LTA process effectiveness in terms of crystal damage recovery as well as dopant diffusion and activation is studied through room-temperature photoluminescence, Secondary Ion Mass Spectroscopy and four-point probe sheet resistance. These studies demonstrate that non-melt LTA with multiple pulses induces high activation without visible diffusion with an effective curing of the implantation-induced crystalline defects. This is made possible thanks to a submicrosecond process timescale coupled to a reasonable number of shots as shown by thermal simulations and simple diffusion estimations.

During rapid thermal processing, nonuniformity of local radiative properties in the wafer front side is now obviously identified to results in thermal dispersion at die scale. This leads to changes in annealing temperature and thus variabilities of electrical behavior and device performances. However, these detrimental contributors remain a hard job to manage. Indeed, both optical and thermal physics are involved, a wide range of scales plays role, and many modeling challenges must be faced to understand and solve such issues. In this study, absorptivity and emissivity of various periodic patterned structures are investigated by optical modeling. It is clearly demonstrated that diffraction plays an important role when gate width dimension or space between gates become small. Then, the radiative properties can be mapped at die scale and hence a thermal simulation can be performed. Our intra-die simulated thermal gradient is in good agreement with experimental results.