Ion-induced leakage current degradation, and single-event burnout may be manifestestations of the same device mechanisms in both silicon carbide power diodes and MOSFETs. In all cases there is a migration of the electrical field from the front body-drain interface to the back epi-drain n+ interface, with a peak exceeding the critical electric field of silicon carbide, causing avalanche generation which enables high short-duration power densities during an approximate 20 psec window after the ion strike. The degradation effect in JBS SiC diodes seems to be independent of the length of the epitaxial region for different voltage-rated diodes.

A phenomenological expression for predicting atmospheric neutron-induced failure rates in silicon carbide (SiC) power devices is presented. This expression that relates the local electric field to terrestrial neutron-induced failure rate is derived using empirical data that show commonalities between failures of different SiC power devices under this type of radiation. We also present a physics-based approach that provides a similar functional form for predicting these failure rates. The proposed closed-form expression is then used to demonstrate the use of this model in predicting failure rates in a hypothetical silicon carbide power device modeled using a technology computer-aided design tool.

Investigations of terrestrial neutron radiationinduced failures in silicon carbide power MOSFETs and diodes indicate that the failures are related to a hole-initiated impact ionization process followed by a thermal transient resulting in the loss of device voltage blocking ability due to the damage of lattice along a filament within the device volume. Irrespective of device type, MOSFET or diode, the start of these failures exhibits the same characteristics, and can be mitigated by decrease in field in device OFF state. These failures with origins in impact ionization and fast thermal transients are fundamentally different from those of bipolar burn-out events, observed in silicon power devices. In addition, once a failure event starts, the failure ends with all terminals shorting.

Ion-induced degradation and catastrophic failures in high-voltage SiC junction barrier Schottky power diodes are investigated. The experimental results agree with earlier data showing discrete jumps in leakage current for individual ions and show that the boundary between leakage current degradation and a single-event-burnout-like effect is a strong function of linear energy transfer and reverse bias. TCAD simulations show high localized electric fields under the Schottky junction, and high temperatures generated directly under the Schottky contact, consistent with the hypothesis that the ion energy causes eutectic-like intermixture at the metal semiconductor interface or localized melting of the silicon carbide lattice.

The short-circuit behavior of power devices is highly relevant for converter design and fault protection. In this paper, the degradation during short circuit of a 10-kV 10-A 4H-SiC MOSFET is investigated at 6 kV dc-link voltage. The study aims to present the behavior of the device during short-circuit transients as it sustains increasing short-circuit pulses during its lifetime. As the short-circuit pulse length increases, degradation of the device can be observed in periodically performed characterizations. The initial degradation seems to be associated with the channel region, and continuous stressing leads to an overall increase in device on-state resistance at the end of the degradation study. Thermal simulation shows that the surface aluminum metalization reached its melting temperature and the top part of the device reaches temperatures above the rated junction temperature. Scanning electron microscope investigation shows aluminum reconstruction and cavities at the contact interface between the aluminum surface metalization and source contacts.

The body diodes of 10kV SiC MOSFETs can be used as anti-parallel diodes in medium voltage converters instead of widely used SiC JBS and PiN diodes. Characterization of switching loss of the body diodes is required to evaluate its candidature for replacement of JBS/PiN diodes. Normally, double pulse test setup is used to observe the reverse recovery behavior of the diodes. But, in high voltage diodes, due to large dv/dt the capacitive current becomes significant, and it superimposes on the reverse recovery current waveform of the diode, misleading the reverse recovery loss data, if the capacitive current is ignored. In this paper, contribution of the capacitive current in the reverse recovery is segregated, which helps in determining actual reverse recovery loss of the diode in double pulse test circuit. Two-slope turn-on characteristic of 15kV SiC IGBT is employed to support the existence of this capacitive current. Using the proposed segregation technique, reverse recovery of the body diode of 10kV SiC MOSFETs is compared with that of 10kV SiC JBS diode.

The impact of the lifetime enhancement process using high temperature thermal oxidation method on 4H-SiC P-GTOs was investigated. 15 kV 4H-SiC P-GTOs with 140 μm thick drift layers, with and without 1450°C lifetime enhancement oxidation (LEO) process, were compared. The LEO process increased the average carrier lifetime in p-type epi layer from 0.9 μs to 6.25 μs, and it was observed that the effectiveness of the lifetime enhancement process was very sensitive to the doping concentration. The device with the LEO process showed a significant reduction in forward voltage drop and a substantially lower holding current, as expected from the carrier lifetime measurements. However, a slight reduction in blocking capability was also observed from the devices treated with LEO process. The common emitter current gain (β) of the wide base test NPN BJT was approximately 10X higher for the wafer with LEO process.

Ultra high voltage (UHV, >15 kV) 4H-silicon carbide (SiC) power devices have the potential to significantly improve the system performance, reliability, and cost of energy conversion systems by providing reduced part count, simplified circuit topology, and reduced switching losses. In this paper, we compare the two MOS based UHV 4H-SiC power switching devices; 15 kV 4H-SiC MOSFETs and 15 kV 4H-SiC n-IGBTs. The 15 kV 4H-SiC MOSFET shows a specific on-resistance of 204 m Omega cm(2) at 25 degrees C, which increased to 570 m Omega cm(2) at 150 degrees C. The 15 kV 4H-SiC MOSFET provides low, temperature-independent, switching losses which makes the device more attractive for applications that require higher switching frequencies. The 15 kV 4H-SiC n-IGBT shows a significantly lower forward voltage drop (V-F), along with reasonable switching performance, which make it a very attractive device for high voltage applications with lower switching frequency requirements. An electrothermal analysis showed that the 15 kV 4H-SiC n-IGBT outperforms the 15 kV 4H-SiC MOSFET for applications with switching frequencies of less than 5 kHz. It was also shown that the use of a carrier storage layer (CSL) can significantly improve the conduction performance of the 15 kV 4H-SiC n-IGBTs.

Recent developments in 3.3 kV to 15 kV 4H-SiC MOSFETs are discussed, and device merits are compared to traditional Silicon IGBT technology, as well as 15 kV SiC n-IGBTs. Performance near theoretical limits was achieved for the 4H-SiC MOSFETs; bipolar 4H-SiC devices were analyzed and were found to handle higher currents at low frequencies.

This paper summarizes the different steps that have been undertaken to design medium voltage power converters using the state-of-the-art 15 kV SiC N-IGBTs. The 11 kV switching characterization results, 11 kV high dv/dt gate driver validation, and the heat-run test results of the SiC IGBT at 10 kV, 550 W/cm2 (active area) have been recently reported as individual topics. In this paper, it is attempted to link all these individual topics and present them as a complete subject from the double pulse tests to the converter design, for evaluating these novel high voltage power semiconductor devices. In addition, the demonstration results of two-level H-Bridge and three-level NPC converters, both at 10 kV dc input, are being presented for the first-time. Lastly, the performance of two-chip IGBT modules for increased current capability and demonstration of three-level poles, built using these modules, at 10 kV dc input with sine-PWM and square-PWM modulation for rectifier and dc-dc stages of a three-phase solid state transformer are presented.

This paper presents the static and dynamic performance of 15 kV SiC IGBTs with 2 um and 5 um field-stop buffer layer thicknesses respectively and compares them with 15 kV SiC MOSFET in term of loss and switching capability. Their switching energy for different gate resistors and temperature have been reported and compared. A 5 kHz 10.5 kW 8 kV boost converter has been built and tested using these three devices respectively. The MOSFET based boost converter has the highest efficiency 99.39% which is the highest reported efficiency for a high voltage SiC device based converter. PLECS loss models can be developed for these devices based on the characterization data to simplify the simulation of a variety circuits or applications which potentially utilize these devices.

Improvements in 900V SiC MOSFET technology have resulted in switches that have extremely low ON resistance in high-speed packages. 900V SiC MOSFETs are promising candidates for hard switched and soft-switched power supply applications due to low ON resistance at higher temperature, a robust low-recovery body diode, avalanche capability and low output stored charge. System designers will be able to use these features to enable novel topologies and achieve large improvements in power density and efficiency. As an example, a 220 W single-stage flyback LED driver is presented, which achieves 40% size reduction over a 650V silicon MOSFET based solution, obtains similar efficiencies and a lower BOM cost.

A high-efficiency, 2.3-MW, medium-voltage, three-level inverter utilizing 4.5-kV Si/SiC (silicon carbide) hybrid modules for wind energy applications is discussed. The inverter addresses recent trends in siting the inverter within the base of multimegawatt turbine towers. A simplified split, three-layer laminated bus structure that maintains low parasitic inductances is introduced along with a low-voltage, high-current test method for determining these inductances. Feed-thru bushings, edge fill methods, and other design features of the laminated bus structure provide voltage isolation that is consistent with the 10.4-kV module isolation levels. Inverter efficiency improvement is a result of the (essential) elimination of the reverse recovery charge present in 4.5-kV Si PIN diodes, which can produce a significant reduction in diode turn-off losses as well as insulated-gate bipolar transistor (IGBT) turn-on losses. The hybrid modules are supplied in industry-standard 140 mm × 130 mm and 190 mm × 130 mm packages to demonstrate direct module substitution into existing inverter designs. A focus on laminated bus/capacitor-bank/module subassembly level switching performance is presented.

A 1 cm x 1 cm 4H-SiC N-IGBT exhibited a blocking voltage of 20.7 kV with a leakage current of 140 μA, which represents the highest blocking voltage reported from a semiconductor power switching device to this date. The device used a 160 μm thick drift layer and a 1 μm thick Field-Stop buffer layer, and showed a VF of 6.4 V at an IC of 20 A, and a differential Ron,sp of 28 mΩ-cm2. Switching measurements with a supply voltage of 8 kV were performed, and a turn-off time of 1.1 μs and turn-off losses of 10.9 mJ were measured at 25°C, for a 8.4 mm x 8.4 mm device with 140 μm drift layer and 2 μm F-S buffer layer. The turn-off losses were reduced by approximately 50% by using a 5 μm F-S buffer layer. A 55 kW, 1.7 kV to 7 kV boost converter operating at 5 kHz was demonstrated using the 4H-SiC N-IGBT, and an efficiency value of 97.8% was reported.

This paper discusses recent trends in wind turbine electrical architecture resulting from utility interconnect and public siting requirements. These trends together with constant need to reduce the cost-of-energy place a premium on wind turbine inverter efficiency. This need is addressed by the use of a medium voltage, three-level inverter with 4HN structure silicon carbide barrier diode located in the clamping diode location. A comparison with a conventional silicon PIN clamping diode is covered in detail.

For the first time, a 1200 V 4H-SiC power MOSFET with a monolithically integrated gate buffer circuit has been demonstrated successfully. The device used a 6x10 15 cm -3 doped, 10 μm thick n-type drift layer to support 1200 V. The gate buffer circuit was built in a p-well, formed by boron ion implantation. The integrated device provided sufficient voltage isolation for the control circuit from the drain of the power MOSFET, and supported internal supply voltages up to 20 V. The operation of the integrated devices was demonstrated. A specific on-resistance ( R on,sp ) of 20 mΩ-cm 2 was observed. The high R on,sp was due to the limitations in NMOS pull-up circuit topology and the body effect in the 4H-SiC NMOSFET. Development of PMOS pull-up devices is recommended for future integration efforts.

The ultrahigh voltage (> 12 kV) SiC IGBTs are promising power semiconductor devices for medium voltage power conversion due to feasibility of simple two-level topologies, reduced component count and extremely high efficiency. However, the current devices generate high dv/dt during switching transitions because of the deep punch-through design. This paper investigates the behavior of dv/dt during the two-slope (different slopes before and after punch-through) turn-on and turn-off voltage transitions of these devices, by varying the device current, temperature and field-stop buffer layer design. It is shown that the dv/dt can be minimized by increasing the gate resistance, by taking the turn-on transition as reference. However, it is found that the increase in gate resistance has very weak impact on dv/dt above the punch-through voltage, and also resulting in significantly increased switching energy loss. It is shown that this problem can be addressed by using a two-stage active gate driver, where the gate current is appropriately controlled to limit the dv/dt over punch-through voltage and to minimize the switching energy loss under the punch-through voltage. Experimental results on 15 kV SiC N-IGBTs with field-stop buffer layer thickness of 2 μm and 5 μm are presented up to 11 kV with a detailed discussion of the results.

This paper reports experimental zero voltage switching (ZVS) characteristics of the state-of-the-art 12 kV SiC N-IGBTs with 2 μm and 5 μm field-stop buffer layer thicknesses. Extensive results up to 7 kV and 150°C are presented for both IGBTs with and without an external snubber capacitor. The 12 kV SiC IGBTs have been found to have significantly larger magnitude of turn-off current bump in comparison to the results reported for the commercial (≤ 6.5 kV) Si IGBTs, because of deep punch-through design. The turn-off current shape is majorly influenced by slower voltage rise before the punch-through, followed by faster voltage rise after the punch-through voltage. In addition, the difference in current gain resulting from different buffer layer thicknesses has considerable effect on the overall switching behavior and energy loss of the two IGBTs. A detailed explanation of all these phenomena is presented along with the considerations for power converter design while employing the ZVS technique with these ultrahigh voltage IGBTs.

Advanced high-voltage (10 kV-15 kV) silicon carbide (SiC) power MOSFETs described in this paper have the potential to significantly impact the system performance, size, weight, high-temperature reliability, and cost of next-generation energy conversion and transmission systems. In this paper, we report our recently developed 10 kV/20 A SiC MOSFETs with a chip size of 8.1 × 8.1 mm2 and a specific on-resistance (RON, SP) of 100 MΩ-cm2 at 25 °C. We also developed 15 kV/10 A SiC power MOSFETs with a chip size of 8 × 8 mm2 and a RON, SP of 204 mQ cm2 at 25 °C. To our knowledge, this 15 kV SiC MOSFET is the highest voltage rated unipolar power switch. Compared to the commercial 6.5 kV Silicon (Si) IGBTs, these 10 kV and 15 kV SiC MOSFETs exhibit extremely low switching losses even when they are switched at 2-3× higher voltage. The benefits of using these 10 kV and 15 kV SiC MOSFETs include simplifying from multilevel to two-level topology and removing the need for time-interleaving by improving the switching frequency from a few hundred Hz for Si based systems to ≥ 10 kHz for hard-switched SiC based systems.