CMOS image sensors (CISs) in high-end mobile devices require wide dynamic range and superior image quality under extremely low light conditions [1]. To implement high-resolution sensors that meet market demand, a back-illuminated stacked sensor with front deep-trench isolation (FDTI) has proven to be effective in implementing submicron pixel sensors with excellent full-well capacity (FWC) and signal-to-noise ratio (SNR) [2, 3]. However, the main risk of FDTI is deterioration of dark temporal noise (TN) as the channel area of in-pixel amplifiers shrinks. In general, in-pixel transistor size is restricted by the presence of high-aspect-ratio DTI. Furthermore, phase-detection auto-focus (PDAF) of the entire imaging area is in high demand for mobile cameras in terms of its high speed and accurate focus, particularly under low-illumination conditions [4, 5]. In this work, a 50Mpixel sensor that satisfies the various characteristics and functions described above is reported. The sensor consists of a quad-PD (Q-cell) with a 0.5μm unit pixel sharing an inter-PD overflow (IPO) path through an intersection of DTIs between neighboring PDs. This shared structure plays an important role in: 1) increasing FWC required for wide dynamic range, 2) increasing conversion gain (CG) by simplifying metal routing of floating diffusion (FD) nodes at DTI intersections, 3) increasing the area of amplifiers in pixels, and 4) increasing sensitivity by removing the doped polysilicon of DTI on an optical axis. In this paper, we present an optimized pixel design and several solutions suitable for deep-submicron pixel sensors that achieve competitive FWC, TN and, sensitivity.

CMOS image sensors (CISs) with deep-submicron pixels are now in high demand, as high-end mobile devices are equipped with multiple camera modules that are used for ultra-high-resolution imaging [1], [2]. The biggest challenges with small pixels are to maintain dynamic range (DR), signal-to-noise ratio (SNR), and sensitivity compatible with a sensor with larger pixels. A back-illuminated stacked sensor with front deep-trench isolation (FDTI) and shallow-trench isolation (STI) for inter-pixel and inter-node isolation respectively appears promising for continuous pixel-size reduction in terms of maximizing DR with large full-well capacity (FWC) while minimizing optical/electrical crosstalk [3]–[5]. However, dark current may increase by strong electric fields (e-field) near defective FDTI interfaces if more doping is applied to a small photodiode (PD) to increase FWC. In addition, the FDTI/STI structure limits the area of in-pixel transistor amplifiers, and it may deteriorate dark temporal noise (TN) as pixel pitch becomes smaller. Furthermore, optical crosstalk between different color filters (CFs) is more problematic as pixel size enters the sub-wavelength scale. In this work, a back-illuminated 64Mpixel CIS with $0.56\mu\mathrm{m}$ -pitched pixels is reported. We present pixel designs and fabrication processes that achieve competitive FWC, dark current, TN, and optical performances with small pixels.

For years, there has been a strong drive for sub-micron pixel development, in spite of reaching the visible light diffraction limit, because a smaller pixel pitch of CMOS image sensors (CISs) is inevitably required for ever-miniaturizing camera modules as mobile devices incorporate more cameras, few of which are dedicated to ultra-high-resolution zoomed images [1]. To that end, image sensor vendors have tried to find new ways to avoid reduction in sensitivity and more crosstalk in the sensor through pixel architecture change and/or fabrication process refinement [2-4]. For example, a 0.7μm pixel sensor was demonstrated with acceptable photodiode (PD) full-well capacity (FWC) of >6,000eas well as signal-to-noise ratio (SNR) of -32dB without optical/electrical crosstalk by employing state-of-the-art full-depth deep-trench isolations (FDTIs). [4] However, further scaling requires elaborate fabrication innovation and layout ideas. At the same time, meeting every aspect of pixel performance compared to the previous generation becomes even more difficult, e.g., with respect to dark or illuminated characteristics, fixed-pattern or temporal noises, etc. The latter, in particular, is associated with in-pixel source-follower (SF) amplifiers. Therefore, electrical performance of scaled in-pixel transistors cannot be overlooked. In this paper, a 32-megpixel (MP) CIS with 0.64μm unit pixels is demonstrated with FDTI design. Innovations in terms of fabrication and design to achieve this performance with scaling are discussed.

Sub-micron pixels have been widely adopted in recent CMOS image sensors to implement high resolution cameras in small form factors, i.e. slim mobile-phones. Even with shrinking pixels, customers demand higher image quality, and the pixel performance must remain comparable to that of the previous generations. Conventionally, to suppress the optical crosstalk between pixels, a metal grid has been used as an isolation structure between adjacent color filters. However, as the pixel size continues to shrink to the sub-micron regime, an optical loss increases because the focal spot size of the pixel’s microlens does not downscale accordingly with the decreasing pixel size due to the diffraction limit: the light absorption inevitably occurs in the metal grid. For the first time, we have demonstrated a new lossless, dielectric-only grid scheme. The result shows 29 % increase in sensitivity and +1.2-dB enhancement in Y-SNR when compared to the previous hybrid metal-and-dielectric grid.

We demonstrated a back-illuminated CMOS image sensor, employing fin field-effect transistors (FinFETs) for in-pixel source-follower (SF) amplifiers. For comparison, two types of SF amplifiers i.e. planar type and FinFET were fabricated and the latter was formed by simply adding a Si etch step on the transistor channel region. Interface trap density was measured to be similar for both, indicating that the etched channel surface of FinFET was comparable to the pristine Si surface of the planar SF. Furthermore, the FinFET SF has increased the trans-conductance (gm) by 37% compared to the planar SF, which also led to improvement of random telegraph signal (RTS) noise by 30% without any image performance degradation. Such improvements are indicative of increase of the effective channel width by the fin structure. We firmly believe that the integration of FinFET transistors to a pixel array accelerates scaling down of a pixel pitch, which is crucial for image sensors in the mobile market. Keywords—CMOS Image Sensors, Fin Field-effect Transistors, Source-follower Amplifiers, Random Telegraph

As the pixel size is scaling down due to the market demand particularly of the mobile CMOS image sensor (CIS) market, the distance between a transfer gate (TG) transistor and a floating diffusion node (FD) is becoming smaller. Consequently, the leakage current at FD nodes by gate-induced drain leakage (GIDL) is a primary source of image defects such as multi-bit white spots particularly where FD nodes are shared for adaptive pixel-level gain control as well as sensitivity improvement at low illumination. In this work, vertically-etched TGs (VTGs) were integrated in a 0.64μm-pixel sensor for better charge transfer from photodiodes as well as smaller pixel area. We found that GIDL of VTGs mainly arises from trap-assisted tunneling (TAT) at the gate controlled FD junction diode with thermal activation. The leakage current exponentially increases with electric field at the drain node of VTGs, which was correlated with overlap capacitance (Cov) between VTG and FD. We were able to mitigate multi-bit white spot defects by optimizing the dry etch condition of VTGs and doping profiles of FD in order to minimize the chip-level variation of Cov. Keywords—CMOS Image Sensor, Transfer Gate Transistor, Gate-induced Drain Leakage, Trap-assisted tunneling.

As the smart mobile device market continues to grow and the number of cameras per device rapidly increases, demand for CMOS image sensors (CIS) also increases. Two major trends in mobile device cameras are: (1) adopting smaller pixels that enable greater pixel count at similar optical format, and (2) bigger pixels for higher image quality. To be more specific, front-facing cameras have a trend towards smaller pixels, while rear main cameras have a trend towards both smaller and bigger pixels. The optical format of front-facing cameras is especially limited due to existing bezel-less or border-less display designs, yet higher resolution still-shot and video (such as 4K UHD) recording is desired. To implement greater pixel count in a limited camera module size, scaling of pixel size is required. The main challenges are to maintain acceptable photodiode full-well capacity (FWC) and sensitivity, while suppressing optical crosstalk [1]. To completely eliminate both electrical and optical crosstalk, deep-trench isolation (DTI) has evolved from early BDTI (Back-side DTI) to current FDTI (Front-side DTI) technology, which is also called full-depth DTI. In this paper, a 44Mpixel CIS with 0.7μm pixels using full-depth DTI is demonstrated.

As the automotive and AI industries are expanding rapidly, global-shutter (GS) image sensors are playing a more significant role in the perception system. More specifically, GS image sensors are required in various fields involving IR, including the face-ID in mobile devices, the driver monitoring system in automotive applications, and factory automation. GS image sensors are necessary for these applications because they can capture freeze-frame images without motion distortion due to their advantage in the pixel operation method. The simultaneous pixel exposure and in-pixel storing capability allow GS image sensors to achieve high-quality imaging, while the sequential pixel exposure and readout of rolling-shutter (RS) image sensors results in image distortion known as the jello effect. For mobile and automotive applications, a small form factor while maintaining a low parasitic light sensitivity (PLS) and low noise is crucial. In conventional backside illuminated (BSI) charge-domain GS image sensors, a light-shielding structure over the storage area must be formed in order to suppress the influence of parasitic light during the readout operation. Therefore, the introduction of such a light-shielding structure reduces the effective photodiode area, which results in a loss of full-well capacity (FWC), light sensitivity of the sensor, and pixel scalability.