We present the recent development of Samsung Foundry’s 300-mm silicon photonics platform for next-generation optical interconnect. This paper reviews the platform overview, the performance of photonic devices and the PDK.

CMOS image sensors (CISs) in high-end mobile devices require wide dynamic range and superior image quality under extremely low light conditions [1]. To implement high-resolution sensors that meet market demand, a back-illuminated stacked sensor with front deep-trench isolation (FDTI) has proven to be effective in implementing submicron pixel sensors with excellent full-well capacity (FWC) and signal-to-noise ratio (SNR) [2, 3]. However, the main risk of FDTI is deterioration of dark temporal noise (TN) as the channel area of in-pixel amplifiers shrinks. In general, in-pixel transistor size is restricted by the presence of high-aspect-ratio DTI. Furthermore, phase-detection auto-focus (PDAF) of the entire imaging area is in high demand for mobile cameras in terms of its high speed and accurate focus, particularly under low-illumination conditions [4, 5]. In this work, a 50Mpixel sensor that satisfies the various characteristics and functions described above is reported. The sensor consists of a quad-PD (Q-cell) with a 0.5μm unit pixel sharing an inter-PD overflow (IPO) path through an intersection of DTIs between neighboring PDs. This shared structure plays an important role in: 1) increasing FWC required for wide dynamic range, 2) increasing conversion gain (CG) by simplifying metal routing of floating diffusion (FD) nodes at DTI intersections, 3) increasing the area of amplifiers in pixels, and 4) increasing sensitivity by removing the doped polysilicon of DTI on an optical axis. In this paper, we present an optimized pixel design and several solutions suitable for deep-submicron pixel sensors that achieve competitive FWC, TN and, sensitivity.

For years, there has been a strong drive for sub-micron pixel development, in spite of reaching the visible light diffraction limit, because a smaller pixel pitch of CMOS image sensors (CISs) is inevitably required for ever-miniaturizing camera modules as mobile devices incorporate more cameras, few of which are dedicated to ultra-high-resolution zoomed images [1]. To that end, image sensor vendors have tried to find new ways to avoid reduction in sensitivity and more crosstalk in the sensor through pixel architecture change and/or fabrication process refinement [2-4]. For example, a 0.7μm pixel sensor was demonstrated with acceptable photodiode (PD) full-well capacity (FWC) of >6,000eas well as signal-to-noise ratio (SNR) of -32dB without optical/electrical crosstalk by employing state-of-the-art full-depth deep-trench isolations (FDTIs). [4] However, further scaling requires elaborate fabrication innovation and layout ideas. At the same time, meeting every aspect of pixel performance compared to the previous generation becomes even more difficult, e.g., with respect to dark or illuminated characteristics, fixed-pattern or temporal noises, etc. The latter, in particular, is associated with in-pixel source-follower (SF) amplifiers. Therefore, electrical performance of scaled in-pixel transistors cannot be overlooked. In this paper, a 32-megpixel (MP) CIS with 0.64μm unit pixels is demonstrated with FDTI design. Innovations in terms of fabrication and design to achieve this performance with scaling are discussed.

We demonstrated a back-illuminated CMOS image sensor, employing fin field-effect transistors (FinFETs) for in-pixel source-follower (SF) amplifiers. For comparison, two types of SF amplifiers i.e. planar type and FinFET were fabricated and the latter was formed by simply adding a Si etch step on the transistor channel region. Interface trap density was measured to be similar for both, indicating that the etched channel surface of FinFET was comparable to the pristine Si surface of the planar SF. Furthermore, the FinFET SF has increased the trans-conductance (gm) by 37% compared to the planar SF, which also led to improvement of random telegraph signal (RTS) noise by 30% without any image performance degradation. Such improvements are indicative of increase of the effective channel width by the fin structure. We firmly believe that the integration of FinFET transistors to a pixel array accelerates scaling down of a pixel pitch, which is crucial for image sensors in the mobile market. Keywords—CMOS Image Sensors, Fin Field-effect Transistors, Source-follower Amplifiers, Random Telegraph

As the pixel size is scaling down due to the market demand particularly of the mobile CMOS image sensor (CIS) market, the distance between a transfer gate (TG) transistor and a floating diffusion node (FD) is becoming smaller. Consequently, the leakage current at FD nodes by gate-induced drain leakage (GIDL) is a primary source of image defects such as multi-bit white spots particularly where FD nodes are shared for adaptive pixel-level gain control as well as sensitivity improvement at low illumination. In this work, vertically-etched TGs (VTGs) were integrated in a 0.64μm-pixel sensor for better charge transfer from photodiodes as well as smaller pixel area. We found that GIDL of VTGs mainly arises from trap-assisted tunneling (TAT) at the gate controlled FD junction diode with thermal activation. The leakage current exponentially increases with electric field at the drain node of VTGs, which was correlated with overlap capacitance (Cov) between VTG and FD. We were able to mitigate multi-bit white spot defects by optimizing the dry etch condition of VTGs and doping profiles of FD in order to minimize the chip-level variation of Cov. Keywords—CMOS Image Sensor, Transfer Gate Transistor, Gate-induced Drain Leakage, Trap-assisted tunneling.

Heterogeneously integrated single-λ and λtunable light sources on bulk-silicon platform are presented. A high wall plug efficiency of 8% up to 70°C is achieved due to efficient heat dissipation capability of bulk-silicon platform.

An O-band DFB laser heterogeneously integrated on bulk-silicon platform is presented. A high wall plug efficiency of over 8% up to 70°C is achieved due to efficient heat dissipation from III/V active region to silicon platform. The single-mode operation is maintained in a wide current range with side-mode suppression ratio over 45dB. This result completes the optical device library suite for the bulk-silicon platform used in most semiconductor products.

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We present photonics technology based on a bulk-Si substrate for cost-sensitive dynamic random-access memory (DRAM) optical interface application. We summarize the progress on passive and active photonic devices using a local-crystallized Si waveguide fabricated by solid phase epitaxy or laser-induced epitaxial growth on bulk-Si substrate. The process of integration of a photonic integrated circuit (IC) with an electronic IC is demonstrated using a 65 nm DRAM periphery process on 300 mm wafers to prove the possibility of seamless integration with various complementary metal-oxide-semiconductor devices. Using the bulk-Si photonic devices, we show the feasibility of high-speed multidrop interface: the Mach–Zehnder interferometer modulators and commercial photodetectors are used to demonstrate four-drop link operation at 10 Gb/s, and the transceiver chips with photonic die and electronic die work for the DDR3 DRAM interface at 1.6 Gb/s under a 1∶4 multidrop configuration.

Optical interconnects may provide solutions to the capacity-bandwidth trade-off of recent memory interface systems. For cost-effective optical memory interfaces, Samsung Electronics has been developing silicon photonics platforms on memory-compatible bulk-Si 300-mm wafers. The waveguide of 0.6 dB/mm propagation loss, vertical grating coupler of 2.7 dB coupling loss, modulator of 10 Gbps speed, and Ge/Si photodiode of 12.5 Gbps bandwidth have been achieved on the bulk-Si platform. 2x6.4 Gbps electrical driver circuits have been also fabricated using a CMOS process.

We report the effects of introducing an undoped Si1-xCx buffer layer between a silicon nanocrystal (nc-Si) active layer and an n-type SiC layer on the performance of the nc-Si light-emitting diodes (LEDs). The electrical property of an nc-Si LED with a buffer layer was greatly improved compared to that of an nc-Si LED without a buffer layer. Moreover, the light output power of the nc-Si LED with a buffer layer was enhanced by a factor of 2. By employing a buffer layer, the efficiency of electron injection into the nc-Si layer was enhanced, which resulted in an increase in the light output power. The data show that the introduction of an undoped Si1-xCx buffer layer is a very effective way to improve the performance of nc-Si LEDs. (C) 2008 The Electrochemical Society.

The enhancement in light extraction efficiency from a periodic micron-scale rugged surface pattern on Si quantum dot light-emitting-diode (Si-QD LED) structures was investigated, both numerically and experimentally. Micron-scale rugged surface patterns were fabricated on the top layer of the Si-QD LED to increase the extraction of light from the active layer. The optimum light extraction condition for a Si-QD LED corresponded to a pattern size/period ratio of ∼0.7. In experiments, the luminescent powers of a Si-QD LED with/without micron-scale surface patterns increase linearly with current density, and the efficiency of light extraction was enhanced by a factor of 2.8.