Several failure analysis case studies have been conducted over the past few years, illustrating the importance of preserving root-cause evidence by means of artifact-free decapsulation. The findings from three of those studies are presented in this article. In one case, the root cause of failure is chlorine contamination. In another, it is a combination of corrosion and metal migration. The third case involves an EOS failure, the evidence of which was hidden under a layer of carbonized mold compound. In addition to case studies, the article also includes images that compare the results of different decapsulation methods.

Failure analysis of automotive semiconductor devices requires highly reliable techniques to guaranty the success of artifact-free decapsulation with high repeatability and reproducibility. With the introduction of new qualification standards, new mold compounds, and new packaging structures, advanced decapsulation tools are needed to enable failure analysis to achieve a high success rate. Microwave Induced Plasma (MIP) machine has been developed as an advanced decapsulation solution. The CF4-free MIP etching ensures artifact-free exposure of bond wires made of new materials, the die, passivation, bond pads, and original failure sites. The high mold compound etching rate, high etching selectivity of mold compound to wire/pad/passivation/die, and the fully automatic process are the unique features of MIP decapsulation. Comparisons are made between acid, conventional plasma with CF4, and CF4-free MIP decapsulation. Multiple case studies are discussed that address challenging automotive semiconductor device decapsulation, including bare copper wire, copper redistribution layer, exposed power copper metal, stitch bond on silver plated leadframe, complex mold compound, Bond-Over-Active-Circuit, eWLB, and localized decapsulation.

With the introduction of new packaging technologies and the great variety of semiconductor devices, new decapsulation tools are needed to improve failure analysis with a higher success rate, and to improve quality control with a higher confidence level. Conventional downstream microwave plasma etchers use CF4 or other fluorine containing compounds in the plasma gas that causes unwanted overetching damage to Si3N4 passivation and the Si die, thus limiting its use in IC package decapsulation. The approach of atmospheric pressure O-2-only Microwave Induced Plasma (MIP) successfully solves the fluorine overetching problem. Comparison between MIP, conventional plasma, acid etching based on several challenging decapsulation applications has shown the great advantage of MIP in preserving the original status of the die, wire bonds, and failure sites. One of the challenging failure analysis cases is Bond-Over-Active-Circuit (BOAC) devices with exposed thin copper metallization traces on top of Si3N4 passivation. The BOAC critical die structures present a challenge to both conventional plasma and acid decapsulation. The use of MIP to solve the BOAC device decapsulation problem will be discussed in detail through multiple case studies. It appears that the MIP machine is the only approach to decapsulate BOAC devices without causing any damage to the exposed copper on passivation critical structure, which demonstrates the failure analysis capabilities of the MIP system.

While carbon nanotubes (CNT) have been suggested as thermal management material for integrated circuits, the thermal properties, and, especially, the thermal boundary resistance (TBR) of as-grown CNT fabricated at low temperature have hardly been investigated. Here, the thermal resistance of CNT vias, with different bundle lengths and diameters fabricated at 500 °C using chemical vapour deposition, are investigated using the 3ω-method. It was found that the thermal resistance hardly changes with length except for the smallest bundle diameter of 2 μm, indicating that the TBR (109–1010 K/W per tube) dominates the thermal conduction. This is in contrast to the electrical resistance and temperature coefficient of resistance, both of which clearly increase with length. From the slope of the thermal resistance versus length of the 2 μm wide bundles, the thermal conductivity of the CNT was estimated to be 1.4–2.8 W/mK. This low thermal conductivity is attributed to the low quality of the samples as determined by Raman spectroscopy.

We review our recent achievements in monolithic 3D-ICs and flexible electronics based on single-grain Si TFTs that are fabricated inside a single-grain with a low-temperature process. Based on pulsed-laser crystallization and submicron sized cavities made in the substrate, amorphous-Si precursor film was converted into poly-Si having grains that are formed on predetermined positions. Using the method called µ-Czochralski process and LPCVD a-Si precursor film, two layers of the SG Si TFT layers with the grains having a diameter of 6µm were vertically stacked with a maximum process temperature of 550°C. Mobility for electrons and holes were 600cm2/Vs and 200cm2/Vs, respectively. As a demonstration of monolithic 3D-ICs, the two SG-TFT layers were successfully implemented into CMOS inverter, 3D 6T-SRAM and single-grain lateral PIN photo-diode with in-pixel amplifier. The SG Si TFTs were applied to flexible electronics. In this case, the a-Si precursor was prepared by doctor-blade coating of liquid-Si based on pure cyclopentasilane (CPS) on a polyimide (PI) substrate with maximum process temperature of 350°C. The µ-Czochralski process provided location-controlled Si grains with a diameter of 3µm and mobilities of 460 and 121cm2/Vs for electrons and holes, respectively, were obtained. The devices on PI were transferred to a plastic foil which can operate with a bending diameter of 6mm. Those results indicate that the SG TFTs are attractive for their use in both monolithic 3D-ICs and flexible electronics.

Carbon nanotubes (CNT) can be an attractive candidate for vertical interconnects (vias) in three-dimensional integrated circuits due to their excellent thermal and electrical properties. To investigate the electrical resistivity of CNT, test vias were fabricated using both a top-down and bottom-up approach. The measured resistivity for the top-down process of 10 mΩ cm is among the better values found in literature. Beside this, the ability to grow CNT directly on single-grain thin-film transistors (SG-TFT) was demonstrated. The electrical performance of the SG-TFT was found not to be influenced by the CNT growth.

The thermal conductivity of as-grown vertical multi-walled carbon nanotubes (CNT) bundles fabricated at low temperature (500 °C) was measured using a vertical 3ω-method. For this, CNT were selectively grown inside an oxide opening and sandwiched between two metal electrodes. The validity of the method was confirmed by both measurements as simulations. The measured thermal conductivity of 1.7-3.5 W/mK is significantly lower than values reported before, which is caused by the low quality of the tubes. This clearly indicates that tube quality will be essential when integrating CNT.

Vertically aligned carbon nanotubes (CNT) were fabricated using a novel CoAlcatalyst at substrate temperatures as low as 350°C and analysed using Raman spectroscopy. Electrical measurement structures were fabricated and characterized using CNT bundles grown at 400°C. The resulting I-V characteristics display a slight non-linearity, likely due to a nonoptimal top contact. The first measurement results indicate CoAl can be an attractive candidate for back-end integration of CNT.

Carbon nanotube (CNT) vias were fabricated at 500 °C with different widths and lengths. The electrical resistance of the CNT vias was measured using four-point probe structures at temperatures between 25 °C and 190 °C. It was found that the temperature coefficient of resistance (TCR) of the CNT vias changes with both length and width. Most of the vias displayed a negative TCR between -300 and -400 ppm/K, against 3900 ppm/K for Cu, but for wider and shorter vias, this value becomes positive. A simple model is introduced, which can explain the length-dependent behavior.

The electrical contact resistance and length dependant resistance of vertically aligned carbon nanotubes (CNT) grown at 500 °C with high tube density (1011 cm-2) are investigated by measuring samples with different CNT lengths. Cross-sectional imaging revealed that the CNT tips are well embedded over a length of several hundred nm. The determined contact resistance of 18 kΩ is low, which is attributed to a combination of CNT tip embedding and tip growth mechanism. When the CNT mean free path determined by Raman spectroscopy is compared with that obtained from the electrical measurements, it shows that multiple walls are conducting in parallel per CNT.

Carbon nanotubes (CNT) can be an attractive candidate for vertical interconnects in 3D monolithic integration, due to their excellent thermal and electrical properties. In this paper we investigate the use of a true bottom-up approach to fabricate CNT vias, for application in 3D monolithic integration. This circumvents metal deposition in high aspect ratio holes, and also allows the use of bundle densification techniques to increase CNT density. Using this approach we fabricated four-point probe electrical measurement structures for both as-grown and densified CNT bundles, and performed I-V measurements. The resulting I-V curves display non-linearities due to a non-Ohmic top contact. The measured resistivities of 10-20 mΩ-cm are among the better values found in literature.

625 nm thick a-Si layer was crystallized by using microsecond pulsed green laser with wavelength of 515 nm. At least 8 m size grains were formed using location controlled single grain technique at room temperature. Energy density window for crystallization and ablation were compared for pulse durations of 300 ns, 1000 ns and 1200 ns.

One of the key challenges in 3D Stacked-ICs (3D-SIC) is to guarantee high product quality at minimal cost. Quality is mostly determined by the applied tests and cost trade-offs. Testing 3D-SICs is very challenging due to several additional test moments for the mid-bond stacks, i.e., partially created stacks. The key question that this paper answers is what is the best test flow to be used in order to optimize the overall cost while realizing the required quality? We first present a framework covering different test flows for 3D Die-to-Wafer (D2W) stacked ICs. Thereafter, we present a cost model that allows us to evaluate these test flows. The impact of different test flows on the overall 3D-SIC cost for several die yields and stack sizes are investigated; a breakdown of the cost into test, manufacturing and packaging cost is also provided. Our simulation results show that both the test cost and the overall cost in D2W stacking strongly depends on the selected test flow; test flows with pre-bond and mid-bond stacking tests (performed during the stacking process) show a higher test cost share, but significantly reduce the overall 3D-SIC cost.

Carbon nanotubes (CNT) can be an attractive candidate for vertical interconnects due to their bottom-up nature and excellent electrical and thermal properties. In this paper we demonstrate low temperature high-density CNT growth and results of electrical characterization. We determined that our CNT contact resistance is low compared to other results in literature, likely caused by a good top contact. The CNT display good uniformity over the wafer and the calculated resistivity of 10 mΩ-cm is among the lowest in literature.

We report high performance single-grain Ge TFTs by μ-Czochralski process. Electron mobilities are 3337cm2/Vs with on/off ratio of 108 @VDS=0.1V. Hole mobilities are 1719cm2/Vs with on/off ratio of 108 @VDS=0.05V. The high mobility is due to improved interface property and tensile stress.

This paper reports on high-performance (100)- and (110)-oriented single-grain thin-film transistors (SG-TFTs) fabricated below 600°C without any seed substrate. Orientation has been controlled by μ-Czochralski process with an excimer laser. The field-effect mobility of the n-channel transistor is 998 cm 2 /V·s for (100) SG-TFTs and 811 cm 2 /V·s for (110) SG-TFTs. The field-effect mobility of the p-channel transistor is 292 cm 2 /V ·s for (100) SG-TFTs and 429 cm 2 /V ·s for (110) SG-TFTs.

Existent flat-panel display is mechanically stiff because it requires external connection of IC chips. At its present stage, displays with a-Si, metal oxide semiconductor or organic TFTs require still external connection of data driver and controllers, because of their low carrier mobilities. We will review our recent progress on direct formation of high speed Si circuits fabricated with a plastic compatible temperature. Large Si grains with a diameter of 4 microns were formed on predetermined positions by a pulsed laser crystallization process with a plastic compatible temperature. High performance transistors were fabricated inside a single Si grain.

In this article, we investigated the high quality SiO2 deposited at 80 degrees C by inductively coupled plasma enhanced chemical vapor deposition (CVD). The interface trap density of 1.48x10(10) cm(-2) eV(-1) and breakdown voltage of 5.6 MV/cm were realized successfully despite the low deposition temperature. Thin film transistors (TFTs) have been fabricated under 100 degrees C by excimer laser annealing. The electron mobility can reach 225 cm(2)/V s. The interface density of SiO2 is comparable with that of thermal oxide. The high quality gate oxide is very suitable for fabricating high performance TFTs for large-area flexible displays on plastics. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3430659] All rights reserved.