Abstract As semiconductor devices continue to scale toward ever-finer pitches, localizing electrical faults in high-density 3D interconnect via chains demands higher imaging resolution than conventional failure analysis setups allow. This article presents an innovative sample preparation approach that addresses this challenge by fabricating low-profile extension electrodes directly on the chip, routing probe pads to the chip edge to free space for high-numerical-aperture objectives — including oil-immersion lenses — during OBIRCH and LICA analysis. Two electrode fabrication methods are described. The approach was successfully demonstrated by localizing a leakage failure in a fine-pitch nanoTSV chain, with TEM analysis confirming partial via fill as the root cause.
Abstract This case study traces the full fault isolation and failure analysis workflow applied to a USB2 interface failure in an Intel H310 platform controller hub following a system-level −2 kV electrostatic discharge event. Beginning with a critical methodological distinction between electrical overstress and ESD — and the different isolation strategies each demands — the article walks through a five-phase workflow: IV curve parametric characterization to confirm resistive shorts on the D+ and D− data lines, confocal scanning acoustic microscopy to rule out gross package damage, lock-in thermography for coarse spatial localization, thermally induced voltage alteration (TIVA) laser probing for transistor-level precision, and CAD overlay correlation to pinpoint the damage site. The findings demonstrate how rigorous hierarchical fault isolation translates a system-level failure into actionable silicon improvement.
Abstract This article introduces a correlative, in-situ methodology that integrates atomic force microscopy directly into the vacuum chamber of a scanning electron microscope or focused ion beam. This method is useful for analyzing increasingly complex structures, particularly for identifying the specific area of electrical failure in devices such as SRAMs, logic, vias, interconnects, and non-visual test failures.
Abstract The EDFAS International Roadmap for Failure Analysis (IRFA) Die-Level Roadmap Council (DLRC) presents its strategic outlook for electrical fault isolation over the next five years, driven by the rapid proliferation of gate-all-around transistors, backside power delivery, heterogeneous integration, and AI-driven design. Across six identified innovation domains — tool development for technology scaling and heterogeneous packaging, workflow evolution, test and diagnostics integration into early design, AI and software tools, and emerging areas — the article maps both the growing limitations of current techniques and the solutions being pursued.
Abstract Long-time EDFAS volunteer leader Ingrid De Wolf reflects on her career and her valuable experiences attending International Symposium for Testing and Failure Analysis events over three decades.
Abstract As part of the International Roadmap for Failure Analysis, the Failure Analysis Outreach Council (FAOC) comprises a selection of dedicated tool users, tool vendors, and academics from across the FA community who are working to bring awareness of the Roadmap and the role of failure analysis to the broader semiconductor ecosystem.
Abstract This article demonstrates the successful implementation of software automated intelligent laser scanning (SAILS) its ability to mask out sites in real-time, and use this mask to modulate laser dwell time. The SAILS workflow has the potential to enable soft defect localization, prioritizing both weak and strong sites, offering a more robust and efficient foundation for future advancements in fault-isolation imaging analysis.
Abstract This article looks at ways to automate FIB-SEM slice and view, dataset post-processing and visualization, and automated defect detection. Virtual slicing in all directions, especially in the top-down view, facilitates the interpretation of defect types and the identification of root causes. Automated slice and view capabilities can save resources and maximize tool utilization.
Abstract Hybrid bonding has emerged as a critical enabler for fine-pitch, high-density 3D interconnects in chiplet-based architectures, but its nanometer-scale tolerances introduce complex defect mechanisms that current inspection and metrology capabilities struggle to address. This article examines inspection challenges across all stages of the hybrid bonding process — surface planarization, activation, alignment, and thermal bonding — and catalogs defect sources, including CMP-induced planarity variations, sub-micron misalignments, interfacial voids, and thermomechanical warpage. It evaluates the performance limits of established nondestructive techniques, such as scanning acoustic microscopy, X-ray computed tomography, optical and infrared metrology, and SEM/FIB cross-sectioning, and finds that no single method can simultaneously deliver nanoscale resolution, full-field coverage, subsurface visibility, and manufacturing-compatible throughput. The article concludes by outlining emerging solutions — including AI-driven defect classification, real-time metrology feedback, and hybrid multi-modal inspection frameworks — as the path toward comprehensive process control in next-generation heterogeneous integration.
This article describes the invention of the Noble Dome: a glove box load-lock that attaches directly to the side of an electron microscope.
This article describes the benefits of defocusing the ion beam for standard FIB processing to mitigate common FIB artifacts. The adjustment leads to several positive outcomes, including increasing the efficiency of material deposition (or even gas-assisted milling) by moving the deposition (milling) regime from precursor-limited to beam-limited, reducing the formation of curtaining by allowing each ion to have a line-of-sight impact on the milling surface and decreasing FIB-induced thermal damage that is largely unaccounted for when milling metals, ceramics, and semiconductors.
This editorial describes the formation and activities of the Expanding Dynamic Growth in Engineering (EDGE) Consortium, which is dedicated to bridging the gap between the fundamental knowledge that students acquire in college and the practical, contextual environment of industry applications.
This article describes a study that investigated the electrical resistivity and residual stress in sputtered indium tin oxide (ITO) films. The study found that resistivity varies spatially with film thickness due to growth conditions and electron scattering, while stress transitions from tensile to compressive with increasing thickness. Understanding and controlling the electric resistivity and residual stress of ITO films is crucial for ensuring the performance and reliability of devices using these films.
This article describes the utility of multimodal spectroscopic metrology tools in characterizing μLED epi-wafers and identifying yield-killing microscopic defects. Techniques applied include photoluminescence mapping, high-resolution photoluminescence, time-resolved photoluminescence, and Raman spectroscopy.
This article presents custom CAD methodologies designed to support efficient failure analysis across disaggregated domains in advanced heterogeneous packages. By enabling synchronized navigation, cross-domain correlation, and real-time visualization across multiple databases, these tools help overcome IP silos and format fragmentation. The result is a significant improvement in traceability, diagnostic precision, and overall failure analysis throughput—driving higher yield and reliability in next-generation semiconductor systems.
This article examines optical fault isolation (OFI) techniques based on heat diffusion for failure analysis of 3D devices, with a focus on thermoreflectance (TR) and laser-induced optical beam-induced resistance change (LI-OBIRCH). TR imaging enables wavelength-selectable probing with structure-dependent thermal coefficients, though performance depends on reducing light source noise. LI-OBIRCH demonstrates 3D analysis capability through a mathematical model and data processing algorithm validated by proof-of-concept experiments on thin 3D test samples. Both techniques show promise for analyzing 3D architectures, including backside power delivery networks and 3D NAND flash memories. Ongoing development addresses physics-related and algorithmic challenges to advance failure analysis capabilities for next-generation semiconductor devices.
This article looks at naive, advanced, and modular retrieval-augmented generation (RAG) architectures for an FA chatbot implementation. This study identified RAG as a suitable adaptation technique that aligns with the specified resource constraints in a cost-effective manner. Even advanced modular RAGs still hallucinate, suggesting that integrating additional adaptation techniques, such as reinforcement learning or targeted fine-tuning, may be necessary for optimal performance.
Chiplets and heterogeneous integration technologies, including advanced packaging, have emerged as a foundational strategy for sustaining the growth of datacenter and edge AI applications. These modular designs are not just a workaround, they represent a paradigm shift in how we architect, manufacture, and scale silicon systems for AI enablement.
This study demonstrates that electron beam-induced degradation critically limits the use of SEM-based nanoprobing for advanced semiconductor devices, particularly for beam-sensitive structures such as FETs in 22 nm FD-SOI technology. Continuous SEM exposure at 100 eV and 200 eV beam energies caused significant, non-reversible threshold voltage shifts. While a 100 eV beam energy substantially slows degradation, it reduces image quality and increases acquisition time, limiting practical advantages during manual probe placement that requires extended imaging. A semi-blind probe positioning approach effectively mitigates beam damage by reducing the required SEM images by approximately two orders of magnitude, enabling reliable probe placement with minimal cumulative exposure.
The Failure Analysis Technology Roadmap was renamed the International Roadmap for Failure Analysis (IRFA). This change reflects its global reach and collaboration with respected organizations including such as IEEE, SRC, and NIST. The new name signifies more than rebranding—it marks IRFA’s rising influence as a trusted global resource for the semiconductor community. This guest column summarizes the mission, vision, and organization of the IRFA initiative.
