This paper proposes a nanoscale ReRAM-based analog Computation-in-Memory, NanoCiM, in which weight-aware X-address scrambling suppresses bit-line current variation caused by IR drop. In analog current-sensing CiM, IR drop due to nanoscale interconnection resistance degrades the bit-line current as a multiply-accumulate (MAC) results. In addition, the bit-line current among bit-lines varies due to the weight data pattern of neural networks in the CiM memory cells. The memory cell current accumulated to bit-line becomes smaller as the distance from the ADC increases due to the interconnection resistance. Weight-aware X-address scrambling shuffles weight data between X-addresses (row-addresses) to reduce the current variation between BLs by taking into account weight data values, and this paper proposes a traveling salesman problem (TSP)-based scrambling method. In addition, the bit-line current decreases by the countercurrent due to IR bounce of the bit-line resistance. By setting the input to the word-line connecting to the gate of transistor of 1T1R ReRAM CiM, the ReRAM transistor is completely turned off and no countercurrent flows from bit-line to source-line. By using NanoCiM, with these strategies, a digit recognition is successful even if the bit-line current variation occurs due to IR drop in half pitch 10-nm interconnection era.

This work investigates the read voltage dependence of discrete shift and spike random telegraph noise (RTN) in the readout current of 40 nm TaOX-based resistive RAM (ReRAM) designed for Computation-in-Memory (CiM) applications. The ReRAM is programmed to eight conductance states and evaluated under five read voltages. Three conventional RTN analysis methods are demonstrated and compared, and a spike extraction scheme is proposed to overcome their limitations. The proposed method reveals pronounced readout current instability in intermediate resistance states, which become more significant at higher read voltages. These findings indicate that lower read voltages are favorable for minimizing readout fluctuations in CiM applications, with 0.2 V identified as the optimal operating voltage for 3-bit ReRAM.

Quantized key-value (KV) cache is a remarkable technology to reduce the memory footprint during large language model (LLM) inference. While multi-level cell (MLC) resistive random-access memory (ReRAM) offers higher density than single-level cell (SLC) ReRAM, its current fluctuation, often induced by random telegraph noise, leads to false detection of cell state and degraded reliability. This work explores a strategy to store quantized KV cache in ReRAM to reduce memory area, while maintaining LLM performance. This study analyzes the error robustness of the three constituent components of the quantized KV cache. The proposal splits the value of each component into the upper bits and the lower bits, then stores the upper bits in SLC ReRAM and the lower bits in MLC ReRAM. This work achieves 49.1% fewer memory cells than the conventional method while maintaining the perplexity at a low level, regardless of LLMs and quantization methods.

To implement the Vision Transformer (ViT) using ReRAM-based Computation-in-Memory (CiM) at edge devices, an iteratively error injected Low-Rank Adapter (Ei-LoRA) has been proposed to mitigate inference accuracy due to quantization and ReRAM device errors with few training parameters. However, there is a trade-off between the LoRA rank in Ei-LoRA and inference accuracy of ViT CiM. While increasing the LoRA rank improves inference accuracy, the number of training parameters also increases. Therefore, by co-optimizing the LoRA rank and inference accuracy, this paper realizes a tiny & error-robust edge ViT CiM that achieves high inference accuracy with fewer training parameters.

This paper optimizes the design of TaOX-based Multi-Level Cell (MLC) ReRAM resistance states for an error correction scheme called Column-wise Weight Value Inversion (Colwin) to reduce the multiply-accumulate value (MACV) errors in analog ReRAM Computation-in-Memory (CiM). The proposed Colwin reduces MACV errors by inverting the weights of neural networks (NNs) to ReRAM resistance states. ReRAM cell current distributions for each resistance state affect the error correction capability of the proposed Colwin. Therefore, in this paper, 4 design cases of ReRAM resistance states are discussed. This paper indicates that the non-uniform ReRAM cell current distribution design is more effective to improve inference accuracy compared to conventional wide-range uniform design. As a result, the proposed Colwin improves inference accuracy by 39.8% those without the proposed Colwin for DR time equivalent to 12 months at 85 degrees C. Moreover, the proposed Colwin reduces the overhead of the flag bits by 78.5% compared to conventional error correcting codes (ECC).

This article proposes an 8 bit truncated carry approximate adder (TCAA), a configurable TCAA (CTCAA) and an explicit bit pruning (EBP) algorithm for SRAM-based digital computation-in-memory to reduce the considerable area and power overhead caused by the adder tree, while maintaining high inference accuracy. The proposed design is verified using 0.18 mu m technology. The TCAA achieves reductions of 38% in area and 40% in power consumption compared with ripple-carry adders. Similarly, the CTCAA achieves 36% and 38% reductions in area and power, respectively. Moreover, with the proposed EBP algorithm, the design achieves 91.9% and 74.3% inference accuracy for the ResNet-18 model on the CIFAR-10 and CIFAR-100 datasets, respectively.

This paper proposes a ReRAM resistance design for ultrahigh-capacity digital memory and analog Computation-in-Memory (CiM). The read-out current of the bit-line is degraded by the interconnection resistance of the bit-line due to IR drop. The bit-line current formulation reveals that the ReRAM resistance should be set as high as 1.0 & times; 105 Omega for the high-capacity digital ReRAM memory. In addition, the ReRAM resistance of LRS and HRS is designed as 1.0 & times; 105 Omega and 1.0 & times; 109 Omega for the high-capacity analog ReRAM CiM.

Abstract This paper proposes a method for predicting the single-wafer wet etching results of Si 3 N 4 using diluted hydrofluoric acid based on Gaussian process regression (GPR) with a limited set of measured data. The GPR model achieves high predictive accuracy even under conditions not included in the training data by optimizing both the hyperparameters and the kernel function that characterizes input correlations. The experimental data are categorized into two groups according to the observed etching-rate patterns, and multiple training datasets were constructed. Models are then trained on each dataset, and their predictive stability is evaluated using two metrics: mean square error and negative log predictive density. Also, the comparison of the prediction accuracy using different types of kernel function in the model is shown. Furthermore, the proposed GPR approach is compared with conventional explicit mathematical modeling methods, thereby demonstrating the superiority of the data-driven approach in capturing the complex dependencies among etching conditions.

This paper proposes a method for predicting the single-wafer wet etching results of Si3N4 using diluted hydrofluoric acid based on Gaussian process regression (GPR) with a limited set of measured data. The GPR model achieves high predictive accuracy even under conditions not included in the training data by optimizing both the hyperparameters and the kernel function that characterizes input correlations. The experimental data are categorized into two groups according to the observed etching-rate patterns, and multiple training datasets were constructed. Models are then trained on each dataset, and their predictive stability is evaluated using two metrics: mean square error and negative log predictive density. Also, the comparison of the prediction accuracy using different types of kernel function in the model is shown. Furthermore, the proposed GPR approach is compared with conventional explicit mathematical modeling methods, thereby demonstrating the superiority of the data-driven approach in capturing the complex dependencies among etching conditions.

Optimizing semiconductor fabrication is challenging due to numerous recipe parameters. This study explores various nozzle operations and wafer rotation speeds to enable selective Si3N4 etching using dilute hydrogen fluoride (DHF). By using measured etching rate (ER), the invertible model dependent on the nozzle scanning period is constructed, enabling determination of etching recipes for the desired ER results. The model is sufficiently accurate for complex scanning patterns, providing a practical tool for process optimization.

This paper proposes a novel algorithm called Variability-aware fine-tuning with Low-rank adapter and Iterative training (VaLI). Previous research applies variability-aware training (VAT) to tackle the difficulty in deploying AI models on non-volatile Computation-in-Memory (CiM) because of the device error introduced from non-idealities of non-volatile memory, e.g. ReRAM. To enable large AI models on the edge device, VaLI introduces Variability-Aware Fine-Tuning (VAFT) which extends the conventional VAT and saves training time. Moreover, VaLI incorporates Low-Rank Adapter (LoRA) to further reduce the excessive computation resources in the training, while proposing iterative training to improve the instability of VAFT with LoRA due to low-rank matrices. The proposed VaLI is evaluated across several models and datasets to showcase its effectiveness by reducing trainable parameters by an average of 90% while maintaining competitive model accuracy against device error.

The step-by-step scheme is proposed to co-design device and system architectural and operational parameters for the summing network with the floating gate-based stochastic neurons. In the proposed scheme, the input signal characteristics are first evaluated to determine the lowest possible error rate. The size of the network is then determined to balance the error rate and the operating energy consumption. The device parameters such as device size and tunnel oxide thickness are set to achieve the desired response time of the neurons under the target input bias. As the source of stochasticity that realizes the stochastic resonance, the temporal noise (electron injection stochasticity (EIS) and random telegraph noise (RTN)), and the spatial distribution are analyzed. Among these three effects, EIS shows the most desirable characteristics for accurate and energy-efficient stochastic resonance operations. Furthermore, the effects of repeated cycling stress are evaluated to understand the reliability of the summing network as a system. In addition, the control scheme of the spatial threshold voltage variation is proposed. By following the proposed step-by-step design procedures, accurate, energy-efficient, and reliable operations of the summing network with the FG-based stochastic neurons can be realized.

In this work, an 8-bit signed approximate adder (SAA) and a quantization-and bit-pruning-aware training method (QBAT) are proposed to reduce the substantial area and power consumption caused by adder trees for digital Computation-in-Memory (DCiM). QBAT achieves efficient bit pruning and minimizes the accuracy loss caused by the approximation. The SAA reduces area and power consumption by 20% and power-delay product (PDP) by 36.7%. With QBAT, the proposed design achieves 95.5% and 96.4% inference accuracy for Resnet-18 and Resnet-50 models on the CIFAR-10 dataset.

Bayesian neural network (BayNN) on ReRAM CiM is realized by exploiting the readout variation of ReRAM devices, such as Random Telegraph Noise (RTN), while conventional BayNNs use Gaussian distributions. Multiple samplings in inference are produced by leveraging the change in each readout current due to RTN. By writing LRS to both sides of a differential pair, the mean and standard deviation of the cells can be programmed to fit the weights of the trained BayNN model. Proposed BayNN with CiM noise achieves performance improvements of 9% and 3% compared with conventional NNs for out-of-distribution detection and adversarial attack detection, respectively.

To embed transformer models on edge devices, Transformer Hetero-Computation-in-Memory (CiM) has been proposed. In this work, a quantization methodology (QM) is proposed to make the entire Transformer Hetero-CiM compact with high inference accuracy. Transformer Hetero-CiM consists of an optimal combination of static random access memory (SRAM) CiM and digital processors for self-attention and multi-level cell (MLC) resistive random access memory (ReRAM) CiM for linear and fully-connected (FC) layers. Proposed QM applies quantization to the inputs and the weights of SRAM CiM and the weights of MLC ReRAM CiM. To further reduce the bit precision of SRAM CiM, Per Layer Block (PLB) quantization is proposed. Proposed PLB quantization introduces blocks to self-attention and optimizes the bit precision of the weights for each block. As a result, Transformer Hetero-CiM with the proposed QM achieves 95.1% inference accuracy while reducing the array area by 90.4% compared to that composed of only SRAM CiM.