In this paper we investigate the impact of N-doping in optimized Ge-rich Ge2Sb2Te5 materials on device programming and storing performance. We integrate these alloys in state-of-the-art Phase-Change Memory (PCM) cells and we analyze the efficiency of the SET operation in N-doped and undoped memory cells, comparing voltage based programming with current based programming. This aspect is extensively investigated through electrical characterization, physico-chemical analysis and electro-thermal simulations. The thermal stability of these devices is finally evaluated and high temperature data retention is granted enabling PCM for embedded applications.

Semiconductor memory has always been an indispensable component of modern electronic systems. The increasing demand for highly scaled memory devices has led to the development of reliable non-volatile memories that are used in computing systems for permanent data storage and are capable of achieving high data rates, with the same or lower power dissipation levels as those of current advanced memory solutions.Among the emerging non-volatile memory technologies, Phase Change Memory (PCM) is the most promising candidate to replace conventional Flash memory technology. PCM offers a wide variety of features, such as fast read and write access, excellent scalability potential, baseline CMOS compatibility and exceptional high-temperature data retention and endurance performances, and can therefore pave the way for applications not only in memory devices, but also in energy demanding, high-performance computer systems. However, some reliability issues still need to be addressed in order for PCM to establish itself as a competitive Flash memory replacement.This work focuses on the study of embedded Phase Change Memory in order to optimize device performance and propose solutions to overcome the key bottlenecks of the technology, targeting high-temperature applications. In order to enhance the reliability of the technology, the stoichiometry of the phase change material was appropriately engineered and dopants were added, resulting in an optimized thermal stability of the device. A decrease in the programming speed of the memory technology was also reported, along with a residual resistivity drift of the low resistance state towards higher resistance values over time.A novel programming technique was introduced, thanks to which the programming speed of the devices was improved and, at the same time, the resistance drift phenomenon could be successfully addressed. Moreover, an algorithm for programming PCM devices to multiple bits per cell using a single-pulse procedure was also presented. A pulse generator dedicated to provide the desired voltage pulses at its output was designed and experimentally tested, fitting the programming demands of a wide variety of materials under study and enabling accurate programming targeting the performance optimization of the technology.

Multilevel Cell programming, i.e. storing multiple bits per memory cell, is a promising way to increase storage density in Phase Change Memory (PCM). In this paper, it is shown that it is possible to program a PCM device to multiple intermediate resistance states by using a single-pulse programming approach, as opposed to time-consuming iterative write algorithms previously reported in the literature. A circuit that generates current programming pulses with characteristics suitable for the specific target resistance state, is presented and simulated. The programmed resistance variation due to the variations in current is also studied and the programmed resistance states distributions are shown to be adequately spaced from each other, thus providing a viable programming solution for obtaining multiple resistance levels per memory cell.

Phase Change Memory (PCM) is the most mature among back-end emerging non-volatile memory concepts. In order to enable embedded PCM applications, the thermal properties of the chalcogenide material have to be boosted, by optimizing its stoichiometry. Ge enrichment of Ge2Sb2Te5 (GST) has been proved to be promising for improving the thermal stability of the technology, but also demonstrates an increase of the low-resistance state (LRS) resistivity as well as a larger resistance drift of this state towards higher resistance over time. This phenomenon can be minimized if an appropriate programming voltage pulse is applied, capable of providing a linearly decreasing temperature profile in the active region of the memory device. In this paper, we discuss the LRS resistance increase of PCM cells based on Ge-rich GST and present a programming voltage profile that is capable of generating a linearly decreasing temperature in the memory cell. A circuit that can generate the desired voltage waveform is presented and simulated in order to prove the functionality of the proposed solution.

In this paper, we discuss the increase of the SET state resistance distribution dispersion in Phase Change Memory (PCM) based on innovative materials, namely Ge-rich Ge2Sb2Te5 (GST). A new programming technique, which consists in linearly decreasing the temperature in the active region of the memory device, is studied and a circuit capable of generating the desired pulse is presented and simulated. Post-layout simulations demonstrate the functionality of the circuit and its potential to be used for the programming of PCM cells based on alternative-to-GST materials.

Phase Change Memory (PCM) is a non-volatile memory technology with wide programming window and continuously improving data retention performance. In order to drive the variable load PCM exhibits, the amplifier providing programming pulses to the cell must be able to accurately control pulse parameters. In this paper, we present a unity gain buffer capable of driving resistive loads varying up to three orders of magnitude. The buffer can replicate voltage pulses of amplitude up to 4.5 V with minimum rise and fall times. The study of the circuit behaviour in high-temperature environments demonstrates its accuracy over a temperature range from -50 °C up to 200 °C, enabling programming of PCM based on innovative materials in applications requiring reliable operation at high temperatures.

In this paper, we propose a novel programming technique, named R-SET pulse, in order to optimize the Low-Resistance State (LRS) performance of Ge-rich phase change materials by overcoming the decrease of crystallization speed caused by Ge enrichment of Ge2Sb2Te5. The R-SET pulse is capable of bringing the cell to its LRS at a lower switching threshold voltage than in the case of conventional programming pulses, thus protecting the cell from potential current overshoots during switching. The functionality of the circuit conceived to generate the R-SET pulse, which operates on a time reference scheme, is discussed. Simulations highlight the tunability of the produced R-SET pulse characteristics.

In this paper, we examine the problem of the drift of the low-resistance state (LRS) in phase change memories based on C or N doped and undoped Ge-rich Ge2Sb2Te5. A novel procedure, named R-SET technique, is proposed to boost the SET speed of these innovative phase change materials by overcoming the decrease of crystallization speed caused by Ge enrichment. The R-SET technique allows, at the same time, an optimized SET programming of the memory cell and the reduction of the LRS drift with respect to standard SET procedures. A circuit that generates the desired R-SET pulse based on a time reference scheme is proposed and discussed.

In this paper, a compact model for PCM cells with a physical approach, which evaluates the state of the cell during and after a programming operation, is described. The model is able to simulate the state of the active material of the cell during the whole programming operation. It takes into account the dynamic of the amorphous cap growth during a RESET operation, as well as the crystallization process, expressed in terms of Crystal Fraction (CF) during a SET operation. The model was validated through comparison with experimental data.

Phase-Change Memory (PCM) is the most mature among back-end emerging memory technologies and a likely candidate for the next generation of non-volatile memories. This paper presents an innovative programming technique for the Low-Resistance State (LRS) in PCM. The technique consists of an appropriately shaped electrical pulse, capable of controlling the power provided to the memory cell in order to enable a linear decrease of the temperature of the cell. The pulse can minimize the distribution dispersion of the LRS, while the pulse falling slope can be externally trimmed to match the crystallization requirements of any material under study. The model of a circuit able to generate the pulse is proposed. Finally, the schematic of a fabricated board with discrete components is presented and experimental results are provided in order to prove the functionality of the system.

In this paper, we investigate the impact of Ge-enrichment coupled to N- or C-doping in Ge2Sb2Te5 based materials on low-resistance state (LRS or SET) performance combined with high-resistance state (HRS or RESET) high-temperature data retention (HTDR) in Phase-Change Memories (PCM). These innovative materials have been integrated in state-of-the-art memory cell prototypes. For the first time, a focus on the trade-off between SET stability (which is affected by resistance drift) and RESET HTDR is proposed. This aspect has been extensively characterized. Through physico-chemical analysis and electrical characterization we demonstrate the need for a specific "programming-current-vs-time-profile" to finally achieve an LRS stable at high-working temperature with programming times compatible with industrial applications. Finally, the reliability of the HRS and the LRS obtained with our optimized programming procedure has been demonstrated through Reflow Soldering Temperature Profile (RSTP) tests. The last result fully enables PCM for embedded applications, in which data integrity after the peak temperature of reflow soldering must be ensured.

Caractérisation et conception d' architectures basées sur des mémoires à changement de phase Les mémoires à base de semi-conducteur sont indispensables pour les dispositifs électroniques actuels. La demande croissante pour des dispositifs mémoires fortement miniaturisées a entraîné le développement de mémoires non volatiles fiables qui sont utilisées dans des systèmes informatiques pour le stockage de données et qui sont capables d'atteindre des débits de données élevés, avec des niveaux de dissipation d'énergie équivalents voire moindres que ceux des technologies mémoires actuelles.Parmi les technologies de mémoires non-volatiles émergentes, les mémoires à changement de phase (PCM) sont le candidat le plus prometteur pour remplacer la technologie de mémoire Flash conventionnelle. Les PCM offrent une grande variété de fonctions, comme une lecture et une écriture rapide, un excellent potentiel de miniaturisation, une compatibilité CMOS et des performances élevées de rétention de données à haute température et d'endurance, et peuvent donc ouvrir la voie à des applications non seulement pour les dispositifs mémoires, mais également pour les systèmes informatiques à hautes performances. Cependant, certains problèmes de fiabilité doivent encore être résolus pour que les PCM se positionnent comme un remplacement concurrentiel de la mémoire Flash.Ce travail se concentre sur l'étude de mémoires à changement de phase intégrées afin d'optimiser leurs performances et de proposer des solutions pour surmonter les principaux points critiques de la technologie, ciblant des applications à hautes températures. Afin d'améliorer la fiabilité de la technologie, la stœchiométrie du matériau à changement de phase a été conçue de façon appropriée et des dopants ont été ajoutés, optimisant ainsi la stabilité thermique. Une diminution de la vitesse de programmation est également rapportée, ainsi qu'un drift résiduel de la résistance de l'état de faiblement résistif vers des valeurs de résistance plus élevées au cours du temps.Une nouvelle technique de programmation est introduite, permettant d'améliorer la vitesse de programmation des dispositifs et, dans le même temps, de réduire avec succès le phénomène de drift en résistance. Par ailleurs, un algorithme de programmation des PCM multi-bits est présenté. Un générateur d'impulsions fournissant des impulsions avec la tension souhaitée en sortie a été conçu et testé expérimentalement, répondant aux demandes de programmation d'une grande variété de matériaux innovants et en permettant la programmation précise et l’optimisation des performances des PCM.