This paper presents a dynamic comparator designed and simulated in a 0.6-mu m indium-gallium-zinc oxide (IGZO) thin-film transistor (TFT) process on a flexible substrate. The proposed circuit operates from a 3-V supply, consumes only 72 mu W of power, and occupies a compact area of 0.042 mm(2). Building upon a double-tailed comparator topology adapted to an all-nTFT process, the design incorporates a fixed-bias preamplifier to enhance offset tolerance and mitigate kickback noise. Post-layout simulations confirm robust performance at clock frequencies up to 200 kHz, with an offset voltage below 10 mV across various process corners. These results highlight the feasibility of implementing high-performance mixed-signal circuits on flexible substrates, enabling applications in large-area, low-cost systems such as sensor interfaces and data converters.
Current mode filters have gained momentum due their better fit to low supply voltage. With respect to the voltage mode counterpart, current mode filters reach a lower input referred noise as the bias current is lowered, enabling significative power saving. Indeed, the noise current is proportional to the bias current. However, the bias current reduction makes arising linearity issue, as the amount of signal current that can be processed is, generally, proportional to the bias current. This is why a push pull current mode filter able to overcome the limitation imposed by the bias current to maximum handleable signal current is proposed. Designed in a 65 nm CMOS technology, the push-pull current mode filter achieves a 3 times higher 1 dB compression point with respect to the simple current mode version. The cost is paid in terms of area, which may increase by up to 50% compared to the simple version, while power consumption remains unaffected.
This paper investigates the hybrid dual-path stepdown (DPSD) dc-dc converter, highlighting the characteristics that make it an attractive alternative to a standard buck converter when a high level of integration and high-frequency operation are both demanded. In particular, the DPSD topology is explored here considering a high frequency (10 to 20 MHz) medium power (1 to 3W) radar automotive application. Moreover, the voltage conversion ratio of the topology is analyzed, pointing out its dependence on power switches' channel resistances and passive components' parasitic resistances through an accurate closedform expression. Finally, the analytical model developed for this topology is verified through simulations, where power switches are implemented with active devices from a standard CMOS process.
Climate change and the depletion of natural resources are driving a shift towards more innovative and sustainable farming practices, with precision farming emerging as a transformative approach. This paper introduces a novel comprehensive electronic platform that integrates ground, aerial and actuation nodes, leveraging IoT-enabled sensors and real-time decision support systems. The platform, which has been successfully tested in a small-scale farm in southern Italy (Apulia region) during a period of severe drought and elevated temperatures, has been designed to automate and optimize agricultural processes (including water and fertilizer application) using a low-cost, scalable solution suitable for both small- and large-scale enterprises. The preliminary results presented herein demonstrate the platform's capability to monitor and optimize crop health. Future work will focus on bridging the gap between field and aerial data, improving data integration and enhancing analytical capabilities through advanced modeling and data mining.
Logic gate drivers are essential components in a wide range of electronic systems, powering everything from mobile phones and workstations to automobiles, industrial automation, and home appliances. Designing these drivers involves challenges like high switching speeds, thermal stability, and power consumption. A failure can disrupt an entire system, so gate drivers need to meet strict specifications. Rigorous production testing is necessary to identify potential failures, ensuring quality and performance in high-demand applications. Testing of devices with Automatic Test Equipment (ATE) requires using different productive hardware that is very expensive and requires a long time to be developed and produced. An error in the design of the final productive hardware may lead to a substantial increase in development costs and the project timeline, which might compromise the time to market of the product itself. This work focuses on the development of a general-purpose board (2ED-GPB) for debugging the main blocks of a test solution for Dual-channel isolated gate drivers. The main purpose of the 2ED-GPB is to verify the proper behavior of newly introduced features of the test circuitry before manufacturing the final hardware to be used in production, allowing for additional cost savings due to possible redesign needed to fix some bugs or optimize some features.
Lightweight and efficient designs of physical unclonable functions (PUFs) and true random number generators (TRNGs) are essential for small embedded devices to enable cryptography applications with secure authentication and randomness. Separate designs of PUFs and TRNGs may incur high costs in hardware, power consumption, and design complexity, as entropy extraction and control mechanisms vary. A compact and robust design combining both functions can significantly reduce the overheads. This work presents a methodology for unifying the design of PUF and TRNG by linking multiple entropy extraction cells to a robust back-end obfuscation using a ring generator. The synthesized design on 180nm CMOS technology costs a small hardware footprint of 95.95 mu m(2) and a minimal energy efficiency of 23.31pJ/bit at 100 Mbps throughput. Additionally, the implementation on FPGA validates the performance of both the PUF and TRNG modes. In PUF mode, the system demonstrated nearly ideal uniqueness and uniformity, achieving 49.98% and 50%, respectively. The random numbers generated in TRNG mode successfully passed the National Institute of Standards and Technology (NIST) SP800-22 random test.
Memristors, first theorized in 1971 and experimentally confirmed in 2009, have attracted substantial research interest due to their unique characteristics. They are particularly significant in applications like neuromorphic computing and memory storage. However, memristive behavior is not always an isolated phenomenon; it can also emerge as a parasitic effect in various electronic devices. Despite this, parasitic memristive effects have received comparatively less attention than traditional circuit components like resistors and capacitors. In this work, we present a model for a device with a Mo/MoSe2/Sb2Se3(10nm)/CdS(2nm)/ITO structure, originally designed as a solar cell, which exhibits memristive behavior. This behavior is analyzed using a slow triangular waveform. Our proposed model extends the conventional single-diode solar cell model by incorporating observed memristive effects as second-order, parasitic elements. Experimental results demonstrate strong agreement with the proposed model, confirming the presence of memristive behavior in the system.
This article presents the application of a previously developed SystemC-AMS Virtual Testing Framework to the complete design of the probe-card, and the development of key test-functions, for a specific industrial automatic test-solution. The Framework, which is based on SystemC-AMS and supported by the COSIDE graphical design environment, is aimed at the optimisation of test-hardware design and test-program coding, by allowing pre-silicon validation of the test-solution. Several improvements have been made to the Framework, such as updated models of automatic test equipment resources and non-linear components, test-flow control via input file, and streamlined implementation of component libraries. By developing the probe-card within the SystemC-AMS Virtual Testing Framework several aspects of its functionality can be investigated, including robustness of the schematic, integrity of the analog and digital signals, solutions for the measurement of notable electrical signals, and an updated current pulse generator based on the modulation of the automatic test equipment resources via active and passive components. The comparison between simulation results and bench measurements performed within the test-program execution on the produced physical probe-card, highlights the capability of the Framework in offering comprehensive support to the development of automatic test-solutions.
This paper investigates the reliability of the 2-bit read operation under temperature variations in the Smart Material Implication (SIMPLY) Logic-in-Memory (LIM) scheme when implemented within a Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM). To be executed, such an operation requires the generation of a proper reference voltage (V-REF). As a result of our study, such a V-REF must take a proportional to absolute temperature (PTAT) behavior to alleviate the detrimental temperature effect on the bit error rate. Accordingly, starting from a prior art subthreshold two-transistor (2T) reference circuit, a V-REF generator employing an 18T topology was designed in the adopted 65-nm CMOS technology and its effect on the reliability of the 2-bit read operation was evaluated across temperatures.
Inspired by the brain's remarkable ability to process information through interconnected neurons, neuromorphic computing aims to emulate the intricate interconnection and information transfer processes characterizing networks of biological neurons. Memristors are widely recognized as the most promising electronic components for enabling the development of neuromorphic computing systems. Their unique ability to emulate synaptic behavior and process information similarly as biological neurons sets them as a cornerstone technology in this field. This review explores the advantages of memristors based on two-dimensional layered halide perovskite (2D LHP) materials, highlighting their ability to mimic synaptic plasticity under a low energy budget. We also discuss recent advancements in 2D LHP memristors and the potential to combine them to build high-performance artificial neural networks. Furthermore, we provide an overview of challenges and future directions for integrating these materials into next-generation neuromorphic systems.
This paper presents an Analog Clock Frequency Divider (CFD) implemented in 0.35 mu m technology, designed for ultra low-power operation in automotive applications during idle-mode. The proposed CFD is designed with a double capacitive system and a comparator to achieve a division factor of about 100. The methodology has been validated through simulations and experimental measurements. The fabricated device achieves a measured division factor of 88. The device operates with an average power consumption of 96 nW at a 3V supply, with 62 nW consumed by the comparator and 34 nW by the capacitive system. The total area occupied by the frequency divider is 7000 mu m2, with 4800 mu m2 dedicated to capacitors. Experimental results show a total variation of 2% over a temperature range from 40 degrees C to 100 degrees C.
In this paper we propose a new empirical formulation for modelling the DC drain-current behaviour of CMOS technology devices for RF applications oriented to quantum computing integrated circuits. The approach is based on the well-known Angelov's model, that has been properly modified to include the capability of reproducing the transistor DC I-V characteristics from ambient down to cryogenic temperature. The approach has been successfully applied to 16-nm FinFET technology, showing very good performance in terms of model accuracy.
Resonant switched-capacitor converters provide high peak efficiency and small area occupation compared to standard inductive-based step-down converters. To enable point-of-load regulation, quasi-resonant control can be used. This control technique changes the energy delivered to the output by modulating the phase shift of the switched-capacitance driving signals. No modification of the power stage topology is needed, thus preserving the converter power density. In this paper, a three-phase quasi-resonant control using a time-based implementation is presented. The proposed circuit exploits a dual-loop control strategy by using a single controller: this is achieved by modulating the common mode and the differential mode of voltage-controlled oscillators. The controller is designed using BCD technology with 180nm CMOS, and its dynamic performance is verified through SIMetrix/SIMPLIS simulations.
This work presents a Time-to-Digital Converter (TDC) for Digital Phase-Locked Loops (DPLLs) applications featuring a dynamic power-reduction technique. The architecture, implemented in a 28-nm CMOS technology with a 0.9-V supply voltage and 250MHz sample rate, is able to reduce its power consumption up to 47% compared to the same TDC without the proposed solution, dissipating a minimum of 33 mu W during normal operation.
Accelerometers in microgravity environments are stimulated by very weak (nm/s2) and very low frequency (< 1 Hz) accelerations, which are therefore very difficult to detect. Thus, the signal processing chain driven by the accelerometer operates at frequencies higher than the band of the 1/f noise as in classical amplification stages. For these reasons the state-of-the-art solutions are often based on analog continuous-time Mixers adopting specific technological choices such as: electrical off-the-shelf transformers directly coupled to the accelerometer and almost flicker-free junction/bipolar Transistors Low Noise Amplifiers. Obviously, this approach severely limits the possibility of miniaturizing analog front-ends disabling the scaling down of the electronic silicon integrated systems. This paper definitively solves the previous problems, proposing a signal processing technique that allows the integration of the front-end in nm-range scaled-down technologies (28 nm CMOS). Specifically, this article focuses on design and development of an analog front-end system composed of an Accelerometer, a (passive) Mixer and a Low Noise Amplifier that allows the reconstruction of signals of the order of 10nm/s(2) on bands of the order of a few Hz. The proposed Nanogravity Accelerometer Analog Front-End (nG-AFE) exhibits 53 dB gain (nm/s(2)to V) at < 1nm/s(2)/v Hz Equivalent acceleration noise Power Spectral Density, performing a final (after digital signal processing reconstruction) 23.5 dB Signal-to-Noise Ratio at 10 nm/s(2) minimum input acceleration.
This paper presents the design of a 10 -bit, $100 \text{MS} / \mathrm{s}\ \mathbf{V}_{\text {CM }}$-based switching Analog-to-Digital Converter (ADC) using the TSMC 40 nm process as a crucial component of the opticalelectrical (O-E) interface in photonic neural networks (PNNs), an emerging technology in next-generation AI. A successive approximation register (SAR) architecture is employed, incorporating a fully custom unit capacitor design in the capacitor array of the digital-to-analog converter. This design minimizes parasitic effects and enhances precision, ensuring efficient signal sampling. The proposed design features a compact core area of $117.84 \mu ~\mathrm{m}\ \times 162.225 \mu ~\mathrm{m}$ and a total chip area of $381.245 \mu ~\mathrm{m} \times 713.61\ \mu \mathrm{m}$. It achieves an $\text{SFDR}_{\text{DC}}=67.9209 ~\text{dB}$, an $\text{SNDR}_{\text{DC}}=55.5257$ dB, and an $\text{ENOB}=8.9312$ when tested with a DC frequency input of 2.25 MHz. At an input frequency close to the Nyquist frequency $(43.85 \text{MHz})$, the ADC attains an SFDR ${ }_{\text{NYQ}}=61.6105$ dB, an $\text{SNDR}_{\text{NYQ}}=51.1768 ~\text{dB}$, and an $\text{ENOB}=8.2088$. The ADC demonstrates a power consumption of $896 \mu ~\mathrm{W}$ at 2.25 MHz input frequency.
This paper presents a complementary (nMOS and pMOS) bootstrapped sampler. The proposed solution is implemented in 28-nm bulk CMOS technology with a 0.9-V supply voltage and integrated with a 250-MS/s Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). Simulations demonstrate that this topology minimizes on-resistance modulation and charge injection effects, leading to a Total Harmonic Distortion (THD) enhancement of -25-dB in the tens of MHz range and -10-dB above 900-MHz compared to the conventional nMOS-based bootstrapped sampler.
